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987 changes: 987 additions & 0 deletions arch/armv7/arch_armv7.cpp

Large diffs are not rendered by default.

35 changes: 35 additions & 0 deletions arch/armv7/armv7_disasm/armv7.c
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,32 @@ static Register regMap[2] = {REG_D0, REG_Q0};
#define SET_REGISTER(x) (1<<((x)))
#define DECODE_DT(s,u) (enum DataType)(1+((((u&1))<<2) | ((s)&3)))

static uint32_t armv7_crc32(uint32_t instructionValue, Instruction* restrict instruction)
{
if ((instructionValue & 0x0f900df0) != 0x01000040)
return 1;

uint32_t size = (instructionValue >> 21) & 3;
uint32_t castagnoli = (instructionValue >> 9) & 1;
if (size == 3)
return 1;

static Operation crc32Operation[2][3] = {
{ ARMV7_CRC32B, ARMV7_CRC32H, ARMV7_CRC32W },
{ ARMV7_CRC32CB, ARMV7_CRC32CH, ARMV7_CRC32CW },
};

instruction->operation = crc32Operation[castagnoli][size];
instruction->cond = (enum Condition)(instructionValue >> 28);
instruction->operands[0].cls = REG;
instruction->operands[0].reg = (enum Register)((instructionValue >> 12) & 0xf);
instruction->operands[1].cls = REG;
instruction->operands[1].reg = (enum Register)((instructionValue >> 16) & 0xf);
instruction->operands[2].cls = REG;
instruction->operands[2].reg = (enum Register)(instructionValue & 0xf);
return 0;
}

static const char* operationString[] = {
"UNDEFINED",
"UNPREDICTABLE",
Expand Down Expand Up @@ -77,6 +103,12 @@ static const char* operationString[] = {
"cdp2",
"clrex",
"clz",
"crc32b",
"crc32cb",
"crc32ch",
"crc32cw",
"crc32h",
"crc32w",
"cmn",
"cmp",
"cps",
Expand Down Expand Up @@ -1081,6 +1113,9 @@ uint32_t armv7_data_processing_and_misc(uint32_t instructionValue, Instruction*
} decode;

decode.value = instructionValue;
if (armv7_crc32(instructionValue, instruction) == 0)
return 0;

if (decode.op == 0)
{
if ((decode.op1 & 0x19) == 0x10) //10xx0
Expand Down
6 changes: 6 additions & 0 deletions arch/armv7/armv7_disasm/armv7.h
Original file line number Diff line number Diff line change
Expand Up @@ -55,6 +55,12 @@ enum Operation {
ARMV7_CDP2,
ARMV7_CLREX,
ARMV7_CLZ,
ARMV7_CRC32B,
ARMV7_CRC32CB,
ARMV7_CRC32CH,
ARMV7_CRC32CW,
ARMV7_CRC32H,
ARMV7_CRC32W,
ARMV7_CMN,
ARMV7_CMP,
ARMV7_CPS,
Expand Down
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