3D Memory Architecture (8×8×8) in Verilog HDL

Project Overview

This repository contains the design and verification of a three-dimensional memory architecture implemented in Verilog HDL. The objective of the project is to model a structured memory system and validate its functionality through digital simulation.

The proposed architecture represents an 8 × 8 × 8 memory structure, providing 512 addressable memory locations, where each location stores an 8-bit data word.

The design supports synchronous read and write operations, controlled by a dedicated control signal and synchronized by a clock signal.

This implementation was developed as part of the Logic Design wiTh HDL (Lab) (CO1026) course at Ho Chi Minh City University of Technology (HCMUT), Vietnam National University Ho Chi Minh City (VNU-HCM).

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Key Features

• 3D memory architecture with 512 addressable locations
• 8-bit data storage per memory cell
• Synchronous read/write operations
• Multi-dimensional addressing (row, column, depth)
• Verified through testbench simulation
• Synthesized and analyzed using Xilinx Vivado

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Key Specifications

Feature	Description
Memory Organization	8 × 8 × 8
Total Memory Cells	512
Data Width	8 bits
Addressing	Row, Column, Depth
Operation Mode	Read / Write
Clock	Synchronous
Language	Verilog HDL
Toolchain	Xilinx Vivado

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System Architecture

The memory module operates synchronously with respect to a clock signal and supports controlled read/write access to memory locations.

Input Signals

Signal	Width	Description
clk	1	System clock
reset	1	System reset
wrt_read	1	Operation control (0 = write, 1 = read)
row_addr	3	Row address
col_addr	3	Column address
depth_addr	3	Depth address
data_in	8	Input data

Output Signal

Signal	Width	Description
data_out	8	Output data

The combination of row, column, and depth addresses uniquely identifies a memory location within the 3D memory structure.

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Synthesized Hardware Architecture

The synthesized hardware architecture generated by Xilinx Vivado is shown below.

The schematic illustrates the combinational logic and memory addressing network created from the Verilog design during synthesis.

Figure 1. Synthesized hardware architecture generated from Vivado.

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Simulation Verification

A testbench was developed to validate the functionality of the memory module.

The verification process includes:

1. Generating a periodic clock signal
2. Applying reset conditions
3. Writing data to multiple memory locations
4. Reading stored values to verify correctness

The simulation waveform obtained from Vivado confirms the correct behavior of both read and write operations.

Figure 2. Simulation waveform demonstrating correct memory read/write operations.

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Memory Organization

The memory system is conceptually organized as a three-dimensional array:

8 × 8 × 8 memory array

This configuration results in:

• 512 memory cells
• 8-bit data width per cell
• Three addressing dimensions (row, column, depth)

This representation provides a structured abstraction for volumetric data storage.

During synthesis, FPGA tools typically map this memory structure into distributed logic or block RAM resources.

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Example Verilog Implementation

reg [7:0] mem [0:7][0:7][0:7];

Each memory location stores 8 bits, and addressing is performed using the row and column indices.

Development Environment

The project was implemented and simulated using the following tools:

• Hardware Description Language: Verilog HDL
• Design and Simulation Tool: Xilinx Vivado

The Vivado simulator was used to observe waveform outputs and verify the functional behavior of the design.

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Repository Structure

3D-Memory-Verilog
│
├── memory3D.v        # Verilog implementation of the memory module
├── tb_memory3D.v     # Testbench for simulation
├── project_2.xpr     # Vivado project file
└── README.md

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Conclusion

This project demonstrates the design and verification of a structured memory system using Verilog HDL.

The implemented architecture successfully supports synchronous read and write operations, and the design was verified through simulation using Xilinx Vivado.

The modular architecture can be extended to support larger memory dimensions or integrated into more complex digital systems such as FPGA-based data processing pipelines.

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Authors

• Phuong Xuong Thinh – Ho Chi Minh City University of Technology
• Le Hien Vinh – Ho Chi Minh City University of Technology