add 128 bit float support to cdorth() (dlang#21293)

Author: WalterBright

compiler/src/dmd/backend/arm/cod1.d

@@ -1341,6 +1341,10 @@ enum CLIB_A
 {
     realToDouble,
     doubleToReal,
+    add,
+    min,
+    mul,
+    div,
     netf2,
 }
 
@@ -1398,6 +1402,38 @@ void getClibFunction(uint clib, ref Symbol* s, ref ClibInfo* cinfo, objfmt_t obj
             break;
         }
 
+        case CLIB_A.add:
+        {
+            string name = "__addtf3";
+            s = symboly(name, mask(32) | mask(33));
+            cinfo.retregs = mask(32);
+            break;
+        }
+
+        case CLIB_A.min:
+        {
+            string name = "__subtf3";
+            s = symboly(name, mask(32) | mask(33));
+            cinfo.retregs = mask(32);
+            break;
+        }
+
+        case CLIB_A.mul:
+        {
+            string name = "__multf3";
+            s = symboly(name, mask(32) | mask(33));
+            cinfo.retregs = mask(32);
+            break;
+        }
+
+        case CLIB_A.div:
+        {
+            string name = "__divtf3";
+            s = symboly(name, mask(32) | mask(33));
+            cinfo.retregs = mask(32);
+            break;
+        }
+
         case CLIB_A.netf2:
         {
             string name = "__netf2";

compiler/src/dmd/backend/arm/cod2.d

@@ -37,7 +37,7 @@ import dmd.backend.oper;
 import dmd.backend.ty;
 import dmd.backend.type;
 import dmd.backend.x86.xmm;
-import dmd.backend.arm.cod1 : loadFromEA, storeToEA, getlvalue;
+import dmd.backend.arm.cod1 : loadFromEA, storeToEA, getlvalue, CLIB_A, callclib;
 import dmd.backend.arm.cod3 : conditionCode, genBranch, gentstreg, movregconst, COND, loadFloatRegConst;
 import dmd.backend.arm.instr;
 
@@ -96,30 +96,47 @@ void cdorth(ref CGstate cg, ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
 
     if (tyfloating(ty1))
     {
-        uint ftype = sz == 2 ? 3 :
-                     sz == 4 ? 0 : 1;
-        switch (e.Eoper)
+        if (sz == 16)                   // 128 bit float
         {
-            // FADD/FSUB (extended register)
-            // http://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#addsub_ext
-            case OPadd:
-                cdb.gen1(INSTR.fadd_float(ftype,Rm,Rn,Rd));     // FADD Rd,Rn,Rm
-                break;
-
-            case OPmin:
-                cdb.gen1(INSTR.fsub_float(ftype,Rm,Rn,Rd));     // FSUB Rd,Rn,Rm
-                break;
-
-            case OPmul:
-                cdb.gen1(INSTR.fmul_float(ftype,Rm,Rn,Rd));     // FMUL Rd,Rn,Rm
-                break;
-
-            case OPdiv:
-                cdb.gen1(INSTR.fdiv_float(ftype,Rm,Rn,Rd));     // FDIV Rd,Rn,Rm
-                break;
+            uint clib;
+            switch (e.Eoper)
+            {
+                case OPadd: clib = CLIB_A.add; break;
+                case OPmin: clib = CLIB_A.min; break;
+                case OPmul: clib = CLIB_A.mul; break;
+                case OPdiv: clib = CLIB_A.div; break;
 
-            default:
-                assert(0);
+                default:
+                    assert(0);
+            }
+            callclib(cdb,e,clib,pretregs,0);
+        }
+        else
+        {
+            const ftype = INSTR.szToFtype(sz);
+            switch (e.Eoper)
+            {
+                // FADD/FSUB (extended register)
+                // http://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#addsub_ext
+                case OPadd:
+                    cdb.gen1(INSTR.fadd_float(ftype,Rm,Rn,Rd));     // FADD Rd,Rn,Rm
+                    break;
+
+                case OPmin:
+                    cdb.gen1(INSTR.fsub_float(ftype,Rm,Rn,Rd));     // FSUB Rd,Rn,Rm
+                    break;
+
+                case OPmul:
+                    cdb.gen1(INSTR.fmul_float(ftype,Rm,Rn,Rd));     // FMUL Rd,Rn,Rm
+                    break;
+
+                case OPdiv:
+                    cdb.gen1(INSTR.fdiv_float(ftype,Rm,Rn,Rd));     // FDIV Rd,Rn,Rm
+                    break;
+
+                default:
+                    assert(0);
+            }
         }
         pretregs = retregs | PSW;
         fixresult(cdb,e,mask(Rd),pretregs);