add 128 bit support to add assignment operators (dlang#21320)

Author: WalterBright

compiler/src/dmd/backend/arm/cod3.d

@@ -68,6 +68,7 @@ nothrow:
 @trusted
 void REGSAVE_save(ref REGSAVE regsave, ref CodeBuilder cdb, reg_t reg, out uint idx)
 {
+    //printf("REGSAVE_save() %s\n", regm_str(mask(reg)));
     assert(reg < 32);    // TODO AArch64 floating point registers
     if (!regsave.alignment)
         regsave.alignment = REGSIZE;
@@ -96,6 +97,7 @@ void REGSAVE_save(ref REGSAVE regsave, ref CodeBuilder cdb, reg_t reg, out uint
 @trusted
 void REGSAVE_restore(const ref REGSAVE regsave, ref CodeBuilder cdb, reg_t reg, uint idx)
 {
+    //printf("REGSAVE_restore() %s\n", regm_str(mask(reg)));
     assert(reg < 32);   // TODO AArch64 floating point registers
     // LDR reg,[BP, #idx]
     code cs;

compiler/src/dmd/backend/arm/cod4.d

@@ -41,7 +41,7 @@ import dmd.backend.oper;
 import dmd.backend.ty;
 import dmd.backend.evalu8 : el_toldoubled;
 import dmd.backend.x86.xmm;
-import dmd.backend.arm.cod1 : getlvalue, loadFromEA, storeToEA;
+import dmd.backend.arm.cod1 : getlvalue, loadFromEA, storeToEA,CLIB_A,callclib;
 import dmd.backend.arm.cod2 : tyToExtend;
 import dmd.backend.arm.cod3 : COND, conditionCode, gentstreg;
 import dmd.backend.arm.instr;
@@ -462,6 +462,7 @@ void floatOpAss(ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
 
     if (e.Eoper == OPnegass)
     {
+        assert(sz1 <= 8);       // not for 128 bit operands
         bool regvar;
         getlvalue(cdb,cs,e1,0);
         if (cs.reg == NOREG)
@@ -538,30 +539,52 @@ void floatOpAss(ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
         cdb.gen(&cs);
     }
 
-    reg_t Rd = reg, Rn = rreg, Rm = reg;
-    uint ftype = INSTR.szToFtype(sz1);
-    switch (e.Eoper)
+    if (sz1 == 16)      // 128 bit float
     {
-        // FADD/FSUB (extended register)
-        // http://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#addsub_ext
-        case OPaddass:
-            cdb.gen1(INSTR.fadd_float(ftype,Rm,Rn,Rd));     // FADD Rd,Rn,Rm
-            break;
+        CLIB_A clib;
+        switch (e.Eoper)
+        {
+            case OPaddass:      clib = CLIB_A.add; break;
+            case OPminass:      clib = CLIB_A.min; break;
+            case OPmulass:      clib = CLIB_A.mul; break;
+            case OPdivass:      clib = CLIB_A.div; break;
+            default:            assert(0);
+        }
+        regm_t idxregs;         // save index registers so we can do the storeToEA() later
+        if (cs.base != NOREG)
+            idxregs |= mask(cs.base);
+        if (cs.index != NOREG)
+            idxregs |= mask(cs.index);
+        regm_t dummy;
+        callclib(cdb,null,clib,dummy,idxregs);
+    }
+    else
+    {
+        reg_t Rd = reg, Rn = rreg, Rm = reg;
+        uint ftype = INSTR.szToFtype(sz1);
+        switch (e.Eoper)
+        {
+            // FADD/FSUB (extended register)
+            // http://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#floatdp2
+            case OPaddass:
+                cdb.gen1(INSTR.fadd_float(ftype,Rm,Rn,Rd));     // FADD Rd,Rn,Rm
+                break;
 
-        case OPminass:
-            cdb.gen1(INSTR.fsub_float(ftype,Rm,Rn,Rd));     // FSUB Rd,Rn,Rm
-            break;
+            case OPminass:
+                cdb.gen1(INSTR.fsub_float(ftype,Rm,Rn,Rd));     // FSUB Rd,Rn,Rm
+                break;
 
-        case OPmulass:
-            cdb.gen1(INSTR.fmul_float(ftype,Rm,Rn,Rd));     // FMUL Rd,Rn,Rm
-            break;
+            case OPmulass:
+                cdb.gen1(INSTR.fmul_float(ftype,Rm,Rn,Rd));     // FMUL Rd,Rn,Rm
+                break;
 
-        case OPdivass:
-            cdb.gen1(INSTR.fdiv_float(ftype,Rm,Rn,Rd));     // FDIV Rd,Rn,Rm
-            break;
+            case OPdivass:
+                cdb.gen1(INSTR.fdiv_float(ftype,Rm,Rn,Rd));     // FDIV Rd,Rn,Rm
+                break;
 
-        default:
-            assert(0);
+            default:
+                assert(0);
+        }
     }
 
     if (!regvar)

compiler/src/dmd/backend/arm/disasmarm.d

@@ -2232,6 +2232,9 @@ void disassemble(uint c) @trusted
             p2 = fregString(rbuf[0 .. 4],prefix,Rd);
             p3 = fregString(rbuf[4 .. 8],prefix,Rn);
             p4 = fregString(rbuf[8 ..12],prefix,Rm);
+
+            uint n = snprintf(buf.ptr, buf.length, "%s_float.html", p1.ptr);
+            url2 = buf[0 .. n];
         }
     }
 

compiler/src/dmd/backend/x86/cod3.d

@@ -4418,7 +4418,7 @@ void prolog_loadparams(ref CodeBuilder cdb, tym_t tyf, bool pushalloc)
                         // STR preg,[sp,#offset]
 //printf("prolog_loadparams sz=%d preg:%d\n", sz, preg);
 //printf("offset(%d) = Fast.size(%d) + BPoff(%d) + EBPtoESP(%d)\n",cast(int)offset,cast(int)cgstate.Fast.size,cast(int)cgstate.BPoff,cast(int)cgstate.EBPtoESP);
-                        uint imm = cast(uint)(offset + localsize + 16);
+                        uint imm = cast(uint)offset;
                         if (mask(preg) & INSTR.FLOATREGS)
                         {
                             uint size, opc;