get tstresult() to work with 128 bit floats (dlang#21306)

Author: WalterBright

compiler/src/dmd/backend/arm/cod1.d

@@ -1231,8 +1231,27 @@ void tstresult(ref CodeBuilder cdb, regm_t regm, tym_t tym, bool saveflag)
 
     if (tyfloating(tym))
     {
-        const ftype = INSTR.szToFtype(sz);
-        cdb.gen1(INSTR.fcmp_float(ftype,0,reg));    // FCMP Vn,#0.0
+        assert(reg & 32);
+        if (tym == TYldouble || tym == TYildouble)
+        {
+            /*
+                fmov q0,reg
+                movi v1.2d,#0   // https://www.scs.stanford.edu/~zyedidia/arm64/movi_advsimd.html
+                bl   __netf2
+                cmp  w0,#0
+             */
+            if (reg != 32)
+                cdb.gen1(INSTR.mov_orr_advsimd_reg(1,reg,32)); // MOV v0,reg
+            cdb.gen1(INSTR.movi_advsimd(1,1,0xE,0,1));          // MOVI V1.2D,0
+            regm_t dummy;
+            callclib(cdb,null,CLIB_A.netf2,dummy,saveflag ? mask(reg) : 0); // __netf2(v0,v1)
+            gentstreg(cdb,0,0);                         // CMP W0,#0
+        }
+        else
+        {
+            const ftype = INSTR.szToFtype(sz);
+            cdb.gen1(INSTR.fcmp_float(ftype,0,reg));    // FCMP Vn,#0.0
+        }
     }
     else
         gentstreg(cdb,reg,sz == 8);                 // CMP reg,#0
@@ -1322,6 +1341,7 @@ enum CLIB_A
 {
     realToDouble,
     doubleToReal,
+    netf2,
 }
 
 private
@@ -1378,6 +1398,14 @@ void getClibFunction(uint clib, ref Symbol* s, ref ClibInfo* cinfo, objfmt_t obj
             break;
         }
 
+        case CLIB_A.netf2:
+        {
+            string name = "__netf2";
+            s = symboly(name, mask(32));
+            cinfo.retregs = mask(32);
+            break;
+        }
+
         default:
             assert(0);
     }
@@ -1408,11 +1436,13 @@ void getClibInfo(uint clib, Symbol** ps, ClibInfo** pinfo, objfmt_t objfmt, exef
 }
 
 /********************************
- * Generate code sequence to call C runtime library support routine.
- *      clib = CLIB_A.xxxx
- *      keepmask = mask of registers not to destroy. Currently can
- *              handle only 1. Should use a temporary rather than
- *              push/pop for speed.
+ * Generate code sequence to call compiler's runtime library support routine.
+ * Params:
+ *      cdb = code sink
+ *      e = elem being tested (null if none)
+ *      clib = CLIB_A.xxxx (function to call)
+ *      pretregs = register(s) to return result in
+ *      keepmask = mask of registers not to destroy. Saves/restores them
  */
 
 @trusted
@@ -1449,7 +1479,8 @@ void callclib(ref CodeBuilder cdb, elem* e, uint clib, ref regm_t pretregs, regm
     cgstate.calledafunc = 1;
 
     cdb.append(cdbpop);
-    fixresult(cdb, e, cinfo.retregs, pretregs);
+    if (e)
+        fixresult(cdb, e, cinfo.retregs, pretregs);
 }
 
 

compiler/src/dmd/backend/arm/disasmarm.d

@@ -295,6 +295,7 @@ void disassemble(uint c) @trusted
     const(char)[] p6 = "";
     const(char)[] p7 = "";
     const(char)[] url = "";
+    const(char)[] url2 = "";
 
     string[4] addsubTab = [ "add", "adds", "sub", "subs" ];
     string[16] condstring =
@@ -2004,6 +2005,28 @@ void disassemble(uint c) @trusted
     else
 
     // Advanced SIMD modified immediate https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asimdimm
+    if (field(ins,31,31) == 0 && field(ins,28,19) == 0x1E0 && field(ins,10,10) == 1)
+    {
+        url = "asimdimm";
+
+        uint Q = field(ins,30,30);
+        uint op = field(ins,29,29);
+        uint abcdefgh = (field(ins,18,16) << 5) | field(ins,9,5);
+        uint cmode = field(ins,15,12);
+        uint o2 = field(ins,11,11);
+        uint Rd = field(ins,4,0);
+
+        if (Q == 1 && op == 1 && cmode == 0xE)
+        {
+            url2 = "movi_advsimd";
+            p1 = "movi";    // https://www.scs.stanford.edu/~zyedidia/arm64/movi_advsimd.html
+            // TODO AArch64 implement https://www.scs.stanford.edu/~zyedidia/arm64/shared_pseudocode.html#impl-shared.AdvSIMDExpandImm.3
+            uint n = snprintf(buf.ptr, cast(uint)buf.length, "v%d.2d,#0x%x", Rd, abcdefgh);
+            p2 = buf[0 .. n];
+        }
+    }
+    else
+
     // Advanced SIMD shift by immediate https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asimdshf
     // Advanced SIMD vector x indexed element https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asimdelem
     // Cryptographic three-register, imm2 https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#crypto3_imm2
@@ -2442,8 +2465,17 @@ void disassemble(uint c) @trusted
     {
         for (; plen < 29; ++plen)
             put(' ');
-        puts(" // https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#");
-        puts(url);
+        puts(" // https://www.scs.stanford.edu/~zyedidia/arm64/");
+        if (url2)
+        {
+            puts(url2);
+            puts(".html");
+        }
+        else
+        {
+            puts("encodingindex.html#");
+            puts(url);
+        }
     }
 }
 }
@@ -2949,8 +2981,9 @@ unittest
 unittest
 {
     int line64 = __LINE__;
-    string[81] cases64 =      // 64 bit code gen
+    string[82] cases64 =      // 64 bit code gen
     [
+        "6F 00 E4 01         movi   v1.2d,#0x0",
         "4E BE 1F C0         mov    v0.16b,v30.16b",
         "D4 20 00 20         brk    #1",
         "D6 3F 00 00         blr    x0",

compiler/src/dmd/backend/arm/instr.d

@@ -707,11 +707,18 @@ struct INSTR
             static uint mov_orr_advsimd_reg(uint Q, reg_t Vn, reg_t Vd) { return orr_advsimd_reg(Q,Vn,Vn,Vd); }
 
     /* Advanced SIMD modified immediate
-     * http://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asimdimm
+     * https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asimdimm
      */
+    static uint asimdimm(uint Q, uint op, uint cmode, uint o2, uint abcdefgh, reg_t Rd)
+    {
+        return (0 << 31) | (Q << 30) | (op << 29) | (0x1E0 << 19) | ((abcdefgh & 0xE0) << (16 - 5)) |
+               (cmode << 12) | (o2 << 11) | (1 << 10) | ((abcdefgh & 0x1F) << 5) | (Rd & 31);
+    }
 
-    // FMOV Rd, Rn  https://www.scs.stanford.edu/~zyedidia/arm64/fmov_float.html
-    static uint fmov(uint ftype, reg_t Vn, reg_t Vd) { return floatdp1(0,0,ftype,0,Vn & 31,Vd & 31); }
+        /* MOVI <Vd>.2D, #<imm> etc.
+         * http://www.scs.stanford.edu/~zyedidia/arm64/movi_advsimd.html
+         */
+        static uint movi_advsimd(uint Q, uint op, uint cmode, uint abcdefgh, reg_t Rd) { return asimdimm(Q,op,cmode,0,abcdefgh,Rd); }
 
     /* Advanced SIMD shift by immediate
      * Advanced SIMD vector x indexed element
@@ -785,6 +792,9 @@ struct INSTR
         return (M << 31) | (S << 29) | (0x1E << 24) | (ftype << 22) | (1 << 21) | (opcode << 15) | (0x10 << 10) | (Rn << 5) | Rd;
     }
 
+    // FMOV Rd, Rn  https://www.scs.stanford.edu/~zyedidia/arm64/fmov_float.html
+    static uint fmov(uint ftype, reg_t Vn, reg_t Vd) { return floatdp1(0,0,ftype,0,Vn & 31,Vd & 31); }
+
     /* FCVT fpreg,fpreg https://www.scs.stanford.edu/~zyedidia/arm64/fcvt_float.html
      */
     static uint fcvt_float(uint ftype, uint opcode, reg_t Vn, reg_t Vd) { return floatdp1(0,0,ftype,opcode,Vn & 31,Vd & 31); }

compiler/src/dmd/backend/x86/cod3.d

@@ -555,7 +555,7 @@ void cod3_stackadj(ref CodeBuilder cdb, int nbytes)
                     Rd;
         cdb.gen1(ins);
         assert(imm12 < (1 << 12));  // only 12 bits allowed
-        assert((imm12 & 0xF) == 0); // 16 byte aligned
+//        assert((imm12 & 0xF) == 0); // 16 byte aligned
         return;
     }
     uint grex = I64 ? REX_W << 16 : 0;