Skip to content

Commit 4ccffa1

Browse files
brendandahlbrendandahl
authored
[FP16] Removed "relaxed" from madd and nmadd. (#8411)
With FP16 there won't be any relaxed instructions because the hardware should always be able to promote the type to F32 so there won't be a double rounding issue.
1 parent 2340f7c commit 4ccffa1

File tree

17 files changed

+104
-124
lines changed

17 files changed

+104
-124
lines changed

‎scripts/gen-s-parser.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -549,15 +549,15 @@
549549
("i16x8.trunc_sat_f16x8_u", "makeUnary(UnaryOp::TruncSatUVecF16x8ToVecI16x8)"),
550550
("f16x8.convert_i16x8_s", "makeUnary(UnaryOp::ConvertSVecI16x8ToVecF16x8)"),
551551
("f16x8.convert_i16x8_u", "makeUnary(UnaryOp::ConvertUVecI16x8ToVecF16x8)"),
552+
("f16x8.madd", "makeSIMDTernary(SIMDTernaryOp::MaddVecF16x8)"),
553+
("f16x8.nmadd", "makeSIMDTernary(SIMDTernaryOp::NmaddVecF16x8)"),
552554

553555
# relaxed SIMD ops
554556
("i8x16.relaxed_swizzle", "makeBinary(BinaryOp::RelaxedSwizzleVecI8x16)"),
555557
("i32x4.relaxed_trunc_f32x4_s", "makeUnary(UnaryOp::RelaxedTruncSVecF32x4ToVecI32x4)"),
556558
("i32x4.relaxed_trunc_f32x4_u", "makeUnary(UnaryOp::RelaxedTruncUVecF32x4ToVecI32x4)"),
557559
("i32x4.relaxed_trunc_f64x2_s_zero", "makeUnary(UnaryOp::RelaxedTruncZeroSVecF64x2ToVecI32x4)"),
558560
("i32x4.relaxed_trunc_f64x2_u_zero", "makeUnary(UnaryOp::RelaxedTruncZeroUVecF64x2ToVecI32x4)"),
559-
("f16x8.relaxed_madd", "makeSIMDTernary(SIMDTernaryOp::RelaxedMaddVecF16x8)"),
560-
("f16x8.relaxed_nmadd", "makeSIMDTernary(SIMDTernaryOp::RelaxedNmaddVecF16x8)"),
561561
("f32x4.relaxed_madd", "makeSIMDTernary(SIMDTernaryOp::RelaxedMaddVecF32x4)"),
562562
("f32x4.relaxed_nmadd", "makeSIMDTernary(SIMDTernaryOp::RelaxedNmaddVecF32x4)"),
563563
("f64x2.relaxed_madd", "makeSIMDTernary(SIMDTernaryOp::RelaxedMaddVecF64x2)"),

‎src/gen-s-parser.inc‎

Lines changed: 47 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -570,12 +570,23 @@ switch (buf[0]) {
570570
}
571571
case 'm': {
572572
switch (buf[7]) {
573-
case 'a':
574-
if (op == "f16x8.max"sv) {
575-
CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::MaxVecF16x8));
576-
return Ok{};
573+
case 'a': {
574+
switch (buf[8]) {
575+
case 'd':
576+
if (op == "f16x8.madd"sv) {
577+
CHECK_ERR(makeSIMDTernary(ctx, pos, annotations, SIMDTernaryOp::MaddVecF16x8));
578+
return Ok{};
579+
}
580+
goto parse_error;
581+
case 'x':
582+
if (op == "f16x8.max"sv) {
583+
CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::MaxVecF16x8));
584+
return Ok{};
585+
}
586+
goto parse_error;
587+
default: goto parse_error;
577588
}
578-
goto parse_error;
589+
}
579590
case 'i':
580591
if (op == "f16x8.min"sv) {
581592
CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::MinVecF16x8));
@@ -592,22 +603,33 @@ switch (buf[0]) {
592603
}
593604
}
594605
case 'n': {
595-
switch (buf[8]) {
596-
case '\0':
597-
if (op == "f16x8.ne"sv) {
598-
CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::NeVecF16x8));
599-
return Ok{};
600-
}
601-
goto parse_error;
602-
case 'a':
603-
if (op == "f16x8.nearest"sv) {
604-
CHECK_ERR(makeUnary(ctx, pos, annotations, UnaryOp::NearestVecF16x8));
605-
return Ok{};
606+
switch (buf[7]) {
607+
case 'e': {
608+
switch (buf[8]) {
609+
case '\0':
610+
if (op == "f16x8.ne"sv) {
611+
CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::NeVecF16x8));
612+
return Ok{};
613+
}
614+
goto parse_error;
615+
case 'a':
616+
if (op == "f16x8.nearest"sv) {
617+
CHECK_ERR(makeUnary(ctx, pos, annotations, UnaryOp::NearestVecF16x8));
618+
return Ok{};
619+
}
620+
goto parse_error;
621+
case 'g':
622+
if (op == "f16x8.neg"sv) {
623+
CHECK_ERR(makeUnary(ctx, pos, annotations, UnaryOp::NegVecF16x8));
624+
return Ok{};
625+
}
626+
goto parse_error;
627+
default: goto parse_error;
606628
}
607-
goto parse_error;
608-
case 'g':
609-
if (op == "f16x8.neg"sv) {
610-
CHECK_ERR(makeUnary(ctx, pos, annotations, UnaryOp::NegVecF16x8));
629+
}
630+
case 'm':
631+
if (op == "f16x8.nmadd"sv) {
632+
CHECK_ERR(makeSIMDTernary(ctx, pos, annotations, SIMDTernaryOp::NmaddVecF16x8));
611633
return Ok{};
612634
}
613635
goto parse_error;
@@ -631,34 +653,12 @@ switch (buf[0]) {
631653
default: goto parse_error;
632654
}
633655
}
634-
case 'r': {
635-
switch (buf[8]) {
636-
case 'l': {
637-
switch (buf[14]) {
638-
case 'm':
639-
if (op == "f16x8.relaxed_madd"sv) {
640-
CHECK_ERR(makeSIMDTernary(ctx, pos, annotations, SIMDTernaryOp::RelaxedMaddVecF16x8));
641-
return Ok{};
642-
}
643-
goto parse_error;
644-
case 'n':
645-
if (op == "f16x8.relaxed_nmadd"sv) {
646-
CHECK_ERR(makeSIMDTernary(ctx, pos, annotations, SIMDTernaryOp::RelaxedNmaddVecF16x8));
647-
return Ok{};
648-
}
649-
goto parse_error;
650-
default: goto parse_error;
651-
}
652-
}
653-
case 'p':
654-
if (op == "f16x8.replace_lane"sv) {
655-
CHECK_ERR(makeSIMDReplace(ctx, pos, annotations, SIMDReplaceOp::ReplaceLaneVecF16x8, 8));
656-
return Ok{};
657-
}
658-
goto parse_error;
659-
default: goto parse_error;
656+
case 'r':
657+
if (op == "f16x8.replace_lane"sv) {
658+
CHECK_ERR(makeSIMDReplace(ctx, pos, annotations, SIMDReplaceOp::ReplaceLaneVecF16x8, 8));
659+
return Ok{};
660660
}
661-
}
661+
goto parse_error;
662662
case 's': {
663663
switch (buf[7]) {
664664
case 'p':

‎src/ir/cost.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -609,8 +609,8 @@ struct CostAnalyzer : public OverriddenVisitor<CostAnalyzer, CostType> {
609609
case LaneselectI16x8:
610610
case LaneselectI32x4:
611611
case LaneselectI64x2:
612-
case RelaxedMaddVecF16x8:
613-
case RelaxedNmaddVecF16x8:
612+
case MaddVecF16x8:
613+
case NmaddVecF16x8:
614614
case RelaxedMaddVecF32x4:
615615
case RelaxedNmaddVecF32x4:
616616
case RelaxedMaddVecF64x2:

‎src/literal.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -727,8 +727,8 @@ class Literal {
727727
Literal convertSToF16x8() const;
728728
Literal convertUToF16x8() const;
729729
Literal swizzleI8x16(const Literal& other) const;
730-
Literal relaxedMaddF16x8(const Literal& left, const Literal& right) const;
731-
Literal relaxedNmaddF16x8(const Literal& left, const Literal& right) const;
730+
Literal maddF16x8(const Literal& left, const Literal& right) const;
731+
Literal nmaddF16x8(const Literal& left, const Literal& right) const;
732732
Literal relaxedMaddF32x4(const Literal& left, const Literal& right) const;
733733
Literal relaxedNmaddF32x4(const Literal& left, const Literal& right) const;
734734
Literal relaxedMaddF64x2(const Literal& left, const Literal& right) const;

‎src/passes/Print.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -790,11 +790,11 @@ struct PrintExpressionContents
790790
case LaneselectI64x2:
791791
o << "i64x2.laneselect";
792792
break;
793-
case RelaxedMaddVecF16x8:
794-
o << "f16x8.relaxed_madd";
793+
case MaddVecF16x8:
794+
o << "f16x8.madd";
795795
break;
796-
case RelaxedNmaddVecF16x8:
797-
o << "f16x8.relaxed_nmadd";
796+
case NmaddVecF16x8:
797+
o << "f16x8.nmadd";
798798
break;
799799
case RelaxedMaddVecF32x4:
800800
o << "f32x4.relaxed_madd";

‎src/passes/RemoveRelaxedSIMD.cpp‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -74,8 +74,6 @@ struct RemoveRelaxedSIMD : WalkerPass<PostWalker<RemoveRelaxedSIMD>> {
7474

7575
void visitSIMDTernary(SIMDTernary* curr) {
7676
switch (curr->op) {
77-
case RelaxedMaddVecF16x8:
78-
case RelaxedNmaddVecF16x8:
7977
case RelaxedMaddVecF32x4:
8078
case RelaxedNmaddVecF32x4:
8179
case RelaxedMaddVecF64x2:

‎src/wasm-binary.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1067,8 +1067,8 @@ enum ASTNodes {
10671067
I32x4RelaxedTruncF32x4U = 0x102,
10681068
I32x4RelaxedTruncF64x2SZero = 0x103,
10691069
I32x4RelaxedTruncF64x2UZero = 0x104,
1070-
F16x8RelaxedMadd = 0x14e,
1071-
F16x8RelaxedNmadd = 0x14f,
1070+
F16x8Madd = 0x14e,
1071+
F16x8Nmadd = 0x14f,
10721072
F32x4RelaxedMadd = 0x105,
10731073
F32x4RelaxedNmadd = 0x106,
10741074
F64x2RelaxedMadd = 0x107,

‎src/wasm-interpreter.h‎

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1710,16 +1710,10 @@ class ExpressionRunner : public OverriddenVisitor<SubType, Flow> {
17101710
case LaneselectI64x2:
17111711
return c.bitselectV128(a, b);
17121712

1713-
case RelaxedMaddVecF16x8:
1714-
if (relaxedBehavior == RelaxedBehavior::NonConstant) {
1715-
return NONCONSTANT_FLOW;
1716-
}
1717-
return a.relaxedMaddF16x8(b, c);
1718-
case RelaxedNmaddVecF16x8:
1719-
if (relaxedBehavior == RelaxedBehavior::NonConstant) {
1720-
return NONCONSTANT_FLOW;
1721-
}
1722-
return a.relaxedNmaddF16x8(b, c);
1713+
case MaddVecF16x8:
1714+
return a.maddF16x8(b, c);
1715+
case NmaddVecF16x8:
1716+
return a.nmaddF16x8(b, c);
17231717
case RelaxedMaddVecF32x4:
17241718
if (relaxedBehavior == RelaxedBehavior::NonConstant) {
17251719
return NONCONSTANT_FLOW;

‎src/wasm.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -587,8 +587,6 @@ enum SIMDTernaryOp {
587587
Bitselect,
588588

589589
// Relaxed SIMD
590-
RelaxedMaddVecF16x8,
591-
RelaxedNmaddVecF16x8,
592590
RelaxedMaddVecF32x4,
593591
RelaxedNmaddVecF32x4,
594592
RelaxedMaddVecF64x2,
@@ -598,6 +596,9 @@ enum SIMDTernaryOp {
598596
LaneselectI32x4,
599597
LaneselectI64x2,
600598
DotI8x16I7x16AddSToVecI32x4,
599+
// FP16
600+
MaddVecF16x8,
601+
NmaddVecF16x8,
601602
};
602603

603604
enum RefAsOp {

‎src/wasm/literal.cpp‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2939,14 +2939,12 @@ static Literal ternary(const Literal& a, const Literal& b, const Literal& c) {
29392939
}
29402940
} // namespace
29412941

2942-
Literal Literal::relaxedMaddF16x8(const Literal& left,
2943-
const Literal& right) const {
2942+
Literal Literal::maddF16x8(const Literal& left, const Literal& right) const {
29442943
return ternary<8, &Literal::getLanesF16x8, &Literal::madd, &toFP16>(
29452944
*this, left, right);
29462945
}
29472946

2948-
Literal Literal::relaxedNmaddF16x8(const Literal& left,
2949-
const Literal& right) const {
2947+
Literal Literal::nmaddF16x8(const Literal& left, const Literal& right) const {
29502948
return ternary<8, &Literal::getLanesF16x8, &Literal::nmadd, &toFP16>(
29512949
*this, left, right);
29522950
}

0 commit comments

Comments
 (0)