Verify icache moudles (#167)

* Changed by Gui-Yue
* Add essential api for missunit agent
* Add tests for existing api
* Build initial env for missunit
* Missunit line coverage reach to 96.7%

* changed by Gui-Yue
* complete tests for all missunit agent.

* * Add missunit functional coverage and related tests.

* complish missunit moudle ut_test

* add doc for missunit

* * Update missunit ut_test functional coverage
* Update doc

* Create test for waylookup

* Accomplish ut_test for icache/waylookup

* Complete tests for waylookup

* * Try to trigger two assert error designed.
* Add initial verification report for missunit.

* * merge commits
* add ut_test for waylookup missunit mainpipe iprefetchpipe

* enable mem-direct for waylookup, missunit and mainpipe.

* Add verify document

* * modify for waylookup
* replace print with toffee.info

* fix some issues in waylookup.

* * add reverse mark
* fix coverage issue

* * fix reverse mark issue
* make line coverage to 100%

* * Add test Coverage Booster to improve line coverage to 100%

Author: Gui-Yue

scripts/build_ut_frontend_icache_mainpipe.py

@@ -8,7 +8,7 @@ def build(cfg):
     internal_signals_path = "scripts/icache_related/icache_mainpipe_internals.yaml"
 
     # export ICacheMainPipe.sv
-    return picker_export(TARGET_NAME, cfg, internal_file=internal_signals_path)
+    return picker_export(TARGET_NAME, cfg, access_mode=1, internal_file=internal_signals_path)
 
 
 def line_coverage_files(cfg):

scripts/build_ut_frontend_icache_missunit.py

@@ -7,7 +7,7 @@ def build(cfg):
     # additional internal signal files
     internal_signals_path = "scripts/icache_related/icache_missunit_internals.yaml"
 
-    return picker_export(TARGET_NAME, cfg, internal_file=internal_signals_path)
+    return picker_export(TARGET_NAME, cfg, access_mode=1, internal_file=internal_signals_path)
 
 
 def line_coverage_files(cfg):

scripts/build_ut_frontend_icache_waylookup.py

@@ -8,7 +8,7 @@ def build(cfg):
     internal_signals_path = "scripts/icache_related/icache_waylookup_internals.yaml"
 
     # export WayLookup.sv
-    return picker_export(TARGET_NAME, cfg, internal_file=internal_signals_path)
+    return picker_export(TARGET_NAME, cfg, access_mode=1, internal_file=internal_signals_path)
 
 
 def line_coverage_files(cfg):

scripts/icache_related/icache_missunit_internals.yaml

@@ -1,30 +1,76 @@
 ICacheMissUnit:
   - "wire _prefetchMSHRs_9_io_req_ready"
   - "wire _prefetchMSHRs_9_io_acquire_valid"
+  - "wire [41:0] _prefetchMSHRs_9_io_resp_bits_blkPaddr"
+  - "wire [7:0] _prefetchMSHRs_9_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_8_io_req_ready"
   - "wire _prefetchMSHRs_8_io_acquire_valid"
+  - "wire [41:0] _prefetchMSHRs_8_io_resp_bits_blkPaddr"
+  - "wire [7:0] _prefetchMSHRs_8_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_7_io_req_ready"
   - "wire _prefetchMSHRs_7_io_acquire_valid"
+  - "wire [41:0] _prefetchMSHRs_7_io_resp_bits_blkPaddr"
+  - "wire [7:0] _prefetchMSHRs_7_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_6_io_req_ready"
   - "wire _prefetchMSHRs_6_io_acquire_valid"
+  - "wire [41:0] _prefetchMSHRs_6_io_resp_bits_blkPaddr"
+  - "wire [7:0] _prefetchMSHRs_6_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_5_io_req_ready"
   - "wire _prefetchMSHRs_5_io_acquire_valid"
+  - "wire [41:0] _prefetchMSHRs_5_io_resp_bits_blkPaddr"
+  - "wire [7:0] _prefetchMSHRs_5_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_4_io_req_ready"
   - "wire _prefetchMSHRs_4_io_acquire_valid"
+  - "wire [41:0] _prefetchMSHRs_4_io_resp_bits_blkPaddr"
+  - "wire [7:0] _prefetchMSHRs_4_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_3_io_req_ready"
   - "wire _prefetchMSHRs_3_io_acquire_valid"
+  - "wire [41:0] _prefetchMSHRs_3_io_resp_bits_blkPaddr"
+  - "wire [7:0] _prefetchMSHRs_3_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_2_io_req_ready"
   - "wire _prefetchMSHRs_2_io_acquire_valid"
+  - "wire [41:0] _prefetchMSHRs_2_io_resp_bits_blkPaddr"
+  - "wire [7:0] _prefetchMSHRs_2_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_1_io_req_ready"
   - "wire _prefetchMSHRs_1_io_acquire_valid"
+  - "wire [41:0] _prefetchMSHRs_1_io_resp_bits_blkPaddr"
+  - "wire [7:0] _prefetchMSHRs_1_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_0_io_req_ready"
   - "wire _prefetchMSHRs_0_io_acquire_valid"
+  - "wire [41:0] _prefetchMSHRs_0_io_resp_bits_blkPaddr"
+  - "wire [7:0] _prefetchMSHRs_0_io_resp_bits_vSetIdx"
 
   - "wire _fetchMSHRs_3_io_req_ready"
   - "wire _fetchMSHRs_3_io_acquire_valid"
+  - "wire [41:0] _fetchMSHRs_3_io_resp_bits_blkPaddr"
+  - "wire [7:0] _fetchMSHRs_3_io_resp_bits_vSetIdx"
   - "wire _fetchMSHRs_2_io_req_ready"
   - "wire _fetchMSHRs_2_io_acquire_valid"
+  - "wire [41:0] _fetchMSHRs_2_io_resp_bits_blkPaddr"
+  - "wire [7:0] _fetchMSHRs_2_io_resp_bits_vSetIdx"
   - "wire _fetchMSHRs_1_io_req_ready"
   - "wire _fetchMSHRs_1_io_acquire_valid"
+  - "wire [41:0] _fetchMSHRs_1_io_resp_bits_blkPaddr"
+  - "wire [7:0] _fetchMSHRs_1_io_resp_bits_vSetIdx"
   - "wire _fetchMSHRs_0_io_req_ready"
-  - "wire _fetchMSHRs_0_io_acquire_valid"
+  - "wire _fetchMSHRs_0_io_acquire_valid"
+  - "wire [41:0] _fetchMSHRs_0_io_resp_bits_blkPaddr"
+  - "wire [7:0] _fetchMSHRs_0_io_resp_bits_vSetIdx"
+
+  - "wire _prefetchDemux_io_chosen"
+  - "wire _prefetchDemux_io_in_ready"
+  - "wire _prefetchDemux_io_in_valid_T_1"
+  - "wire _fetchDemux_io_in_ready"
+  - "wire _fetchDemux_io_in_valid_T_1"
+
+  - "wire prefetchHit"
+  - "wire fetchHit"
+
+  - "wire last_fire"
+  - "reg last_fire_r"
+
+  - "wire _priorityFIFO_io_enq_ready"
+  - "wire _priorityFIFO_io_enq_valid_T_probe"
+  - "wire _priorityFIFO_io_deq_valid"
+  - "wire _priorityFIFO_io_deq_ready_T"
+  - "wire _priorityFIFO_io_deq_bits"