From 6b0f78c0a918d5a79767a25ca32d568abc4eabed Mon Sep 17 00:00:00 2001 From: Gui-Yue Date: Sat, 28 Feb 2026 21:24:05 +0800 Subject: [PATCH] add coverage mapping, fix internal signal access, improve line coverage, and stabilize failing checks --- .../build_ut_frontend_icache_iprefetchpipe.py | 66 ++++- .../icache/iprefetchpipe/env/watch_point.py | 262 ++++++++++++++++-- .../test/iprefetchpipe_fixture.py | 5 +- .../iprefetchpipe/test/iprefetchpipe_test.py | 161 ++++++++++- 4 files changed, 461 insertions(+), 33 deletions(-) diff --git a/scripts/build_ut_frontend_icache_iprefetchpipe.py b/scripts/build_ut_frontend_icache_iprefetchpipe.py index 4f870273..4325d472 100644 --- a/scripts/build_ut_frontend_icache_iprefetchpipe.py +++ b/scripts/build_ut_frontend_icache_iprefetchpipe.py @@ -3,14 +3,74 @@ TARGET_NAME = "IPrefetchPipe" +def _extract_signals_with_ports(verilog_file: str, output_file: str) -> None: + """Export both internal declarations and IO ports for mem-direct access.""" + import os + import re + + decl = re.compile( + r"^\s*(?:(input|output|inout)\s+)?(?:(wire|reg|logic)\s+)?(\[[^\]]+\]\s+)?" + r"([A-Za-z_][\w$]*(?:\s*,\s*[A-Za-z_][\w$]*)*)\s*(?:[,;]|=)" + ) + + seen = set() + extracted = [] + + with open(verilog_file, "r", encoding="utf-8") as f: + for raw in f: + line = raw.strip() + if not line or line.startswith("//"): + continue + m = decl.match(raw) + if not m: + continue + direction, sig_type, width, names = m.groups() + # Skip non-declaration statements accidentally matched. + if direction is None and sig_type is None: + continue + signal_type = sig_type or "wire" + if signal_type == "reg": + signal_type = "logic" + width = (width or "").strip() + for name in [x.strip() for x in names.split(",")]: + if name.startswith("_GEN") or name in seen: + continue + seen.add(name) + if width: + extracted.append(f' - "{signal_type} {width} {name}"') + else: + extracted.append(f' - "{signal_type} {name}"') + + module_name = os.path.splitext(os.path.basename(verilog_file))[0] + with open(output_file, "w", encoding="utf-8") as f: + f.write(f"{module_name}:\n") + f.write("\n".join(extracted)) + f.write("\n") + + def build(cfg): - # additional internal signal files - internal_signals_path = "scripts/icache_related/icache_iprefetchpipe_internals.yaml" + # Use mem-direct mode and export a complete internal list so + # GetInternalSignal(use_vpi=False) can be used safely in tests. + import os + from tempfile import NamedTemporaryFile + from comm import get_rtl_dir # verilator arguments verilator_args = "--x-initial;0" - return picker_export(TARGET_NAME, cfg, internal_file=internal_signals_path, vflags=verilator_args) + with NamedTemporaryFile("w+", prefix=TARGET_NAME, suffix=".yaml") as internal: + internal_signals_path = internal.name + rtl_file = get_rtl_dir(f"{TARGET_NAME}.sv", cfg=cfg) + if not os.path.exists(rtl_file): + rtl_file = get_rtl_dir(f"{TARGET_NAME}.v", cfg=cfg) + _extract_signals_with_ports(rtl_file, internal_signals_path) + return picker_export( + TARGET_NAME, + cfg, + access_mode=1, + internal_file=internal_signals_path, + vflags=verilator_args, + ) def line_coverage_files(cfg): diff --git a/ut_frontend/icache/iprefetchpipe/env/watch_point.py b/ut_frontend/icache/iprefetchpipe/env/watch_point.py index 6f1b976a..369dfd45 100644 --- a/ut_frontend/icache/iprefetchpipe/env/watch_point.py +++ b/ut_frontend/icache/iprefetchpipe/env/watch_point.py @@ -1,5 +1,6 @@ import toffee.funcov as fc from toffee.funcov import CovGroup +from comm import module_name_with from dut.IPrefetchPipe import DUTIPrefetchPipe def check_prefetch_start_address(dut: DUTIPrefetchPipe) -> bool: @@ -40,6 +41,10 @@ def define_iprefetchpipe_coverage(bundle, dut): dut: DUT对象，用于访问内部信号 """ g = CovGroup("IPrefetchPipe_Coverage") + + # 反标 + def _M(name): + return module_name_with(name, "../../test/iprefetchpipe_test") # 创建IPrefetchPipe内部信号字典，便于访问（根据实际可访问的信号更新） IPrefetchPipe_dict = { @@ -91,10 +96,10 @@ def define_iprefetchpipe_coverage(bundle, dut): "s2_mmio_0": "IPrefetchPipe_top.IPrefetchPipe.s2_mmio_0", "s2_mmio_1": "IPrefetchPipe_top.IPrefetchPipe.s2_mmio_1", # 仲裁器相关信号 - "toMSHRArbiter_io_in_0_valid": "IPrefetchPipe._toMSHRArbiter_io_in_0_valid_T_2", - "toMSHRArbiter_io_in_1_valid": "IPrefetchPipe._toMSHRArbiter_io_in_1_valid_T_2", - "toMSHRArbiter_io_in_0_ready": "IPrefetchPipe._toMSHRArbiter_io_in_0_ready", - "toMSHRArbiter_io_in_1_ready": "IPrefetchPipe._toMSHRArbiter_io_in_1_ready", + "toMSHRArbiter_io_in_0_valid": "IPrefetchPipe_top.IPrefetchPipe._toMSHRArbiter_io_in_0_valid_T_2", + "toMSHRArbiter_io_in_1_valid": "IPrefetchPipe_top.IPrefetchPipe._toMSHRArbiter_io_in_1_valid_T_2", + "toMSHRArbiter_io_in_0_ready": "IPrefetchPipe_top.IPrefetchPipe._toMSHRArbiter_io_in_0_ready", + "toMSHRArbiter_io_in_1_ready": "IPrefetchPipe_top.IPrefetchPipe._toMSHRArbiter_io_in_1_ready", # CP10刷新机制相关内部信号 "from_bpu_s0_flush_probe": "IPrefetchPipe_top.IPrefetchPipe.from_bpu_s0_flush_probe", "from_bpu_s1_flush_probe": "IPrefetchPipe_top.IPrefetchPipe.from_bpu_s1_flush_probe", @@ -171,6 +176,29 @@ def define_iprefetchpipe_coverage(bundle, dut): }, name="CP1_Prefetch_Request_Reception" ) + g.mark_function( + "CP1_Prefetch_Request_Reception", + _M( + [ + "test_cp1_receive_prefetch_requests", + "test_prefetch_request_apis", + "test_basic_control_apis", + "test_smoke", + "test_full_iprefetch_pipeline", + ] + ), + bin_name=[ + "CP1_1_1_hw_prefetch_can_continue", + "CP1_1_2_hw_prefetch_rejected_invalid", + "CP1_1_3_hw_prefetch_rejected_not_ready", + "CP1_1_5_hw_prefetch_single_cacheline", + "CP1_1_6_hw_prefetch_double_cacheline", + "CP1_2_1_sw_prefetch_can_continue", + "CP1_2_2_sw_prefetch_rejected_invalid", + "CP1_2_5_sw_prefetch_single_cacheline", + "CP1_2_6_sw_prefetch_double_cacheline", + ], + ) # ================================================================= # CP 2: 接收来自ITLB的响应并处理结果覆盖点 @@ -316,6 +344,34 @@ def define_iprefetchpipe_coverage(bundle, dut): }, name="CP2_ITLB_Response_Processing" ) + g.mark_function( + "CP2_ITLB_Response_Processing", + _M( + [ + "test_cp2_receive_itlb_responses", + "test_itlb_interaction_apis", + "test_full_iprefetch_pipeline", + ] + ), + bin_name=[ + "CP2_1_1_itlb_normal_paddr_return_port0", + "CP2_1_1_itlb_normal_paddr_return_dual_port", + "CP2_1_2_itlb_miss_retry_port0", + "CP2_1_2_itlb_miss_retry_port1", + "CP2_1_2_itlb_retry_completed", + "CP2_2_1_itlb_page_fault_port0", + "CP2_2_2_itlb_guest_page_fault_port0", + "CP2_2_3_itlb_access_fault_port0", + "CP2_2_1_itlb_page_fault_port1", + "CP2_2_2_itlb_guest_page_fault_port1", + "CP2_2_3_itlb_access_fault_port1", + "CP2_3_1_gpf_return_gpaddr_port0", + "CP2_3_1_gpf_return_gpaddr_port1", + "CP2_3_2_gpf_vs_nonleaf_pte", + "CP2_4_return_pbmt_info_port0", + "CP2_4_return_pbmt_info_port1", + ], + ) # ================================================================= # CP 3: 接收来自IMeta（缓存元数据）的响应并检查缓存命中覆盖点 @@ -337,15 +393,15 @@ def define_iprefetchpipe_coverage(bundle, dut): "meta_valid_1_way3": bundle.io._metaRead._fromIMeta._entryValid._1._3, # 端口0的4路标签（通过GetInternalSignal获取） - "meta_tag_0_way0": dut.GetInternalSignal("IPrefetchPipe_top.IPrefetchPipe.io_metaRead_fromIMeta_metas_0_0_tag", use_vpi=False), - "meta_tag_0_way1": dut.GetInternalSignal("IPrefetchPipe_top.IPrefetchPipe.io_metaRead_fromIMeta_metas_0_1_tag", use_vpi=False), - "meta_tag_0_way2": dut.GetInternalSignal("IPrefetchPipe_top.IPrefetchPipe.io_metaRead_fromIMeta_metas_0_2_tag", use_vpi=False), - "meta_tag_0_way3": dut.GetInternalSignal("IPrefetchPipe_top.IPrefetchPipe.io_metaRead_fromIMeta_metas_0_3_tag", use_vpi=False), + "meta_tag_0_way0": dut.GetInternalSignal("IPrefetchPipe_top.io_metaRead_fromIMeta_metas_0_0_tag", use_vpi=False), + "meta_tag_0_way1": dut.GetInternalSignal("IPrefetchPipe_top.io_metaRead_fromIMeta_metas_0_1_tag", use_vpi=False), + "meta_tag_0_way2": dut.GetInternalSignal("IPrefetchPipe_top.io_metaRead_fromIMeta_metas_0_2_tag", use_vpi=False), + "meta_tag_0_way3": dut.GetInternalSignal("IPrefetchPipe_top.io_metaRead_fromIMeta_metas_0_3_tag", use_vpi=False), # 端口1的4路标签 - "meta_tag_1_way0": dut.GetInternalSignal("IPrefetchPipe_top.IPrefetchPipe.io_metaRead_fromIMeta_metas_1_0_tag", use_vpi=False), - "meta_tag_1_way1": dut.GetInternalSignal("IPrefetchPipe_top.IPrefetchPipe.io_metaRead_fromIMeta_metas_1_1_tag", use_vpi=False), - "meta_tag_1_way2": dut.GetInternalSignal("IPrefetchPipe_top.IPrefetchPipe.io_metaRead_fromIMeta_metas_1_2_tag", use_vpi=False), - "meta_tag_1_way3": dut.GetInternalSignal("IPrefetchPipe_top.IPrefetchPipe.io_metaRead_fromIMeta_metas_1_3_tag", use_vpi=False), + "meta_tag_1_way0": dut.GetInternalSignal("IPrefetchPipe_top.io_metaRead_fromIMeta_metas_1_0_tag", use_vpi=False), + "meta_tag_1_way1": dut.GetInternalSignal("IPrefetchPipe_top.io_metaRead_fromIMeta_metas_1_1_tag", use_vpi=False), + "meta_tag_1_way2": dut.GetInternalSignal("IPrefetchPipe_top.io_metaRead_fromIMeta_metas_1_2_tag", use_vpi=False), + "meta_tag_1_way3": dut.GetInternalSignal("IPrefetchPipe_top.io_metaRead_fromIMeta_metas_1_3_tag", use_vpi=False), # 物理地址（用于提取标签进行比较） "s1_req_paddr_0": dut.GetInternalSignal("IPrefetchPipe_top.IPrefetchPipe.s1_req_paddr_0", use_vpi=False), @@ -443,6 +499,31 @@ def define_iprefetchpipe_coverage(bundle, dut): }, name="CP3_IMeta_Response_And_Cache_Hit_Check" ) + g.mark_function( + "CP3_IMeta_Response_And_Cache_Hit_Check", + _M( + [ + "test_cp3_receive_imeta_responses_and_cache_hit_check", + "test_meta_array_apis", + "test_all_bundle_signals", + "test_full_iprefetch_pipeline", + ] + ), + bin_name=[ + "CP3_1_tag_compare_and_valid_check_port0_way0", + "CP3_1_tag_compare_and_valid_check_port0_way1", + "CP3_1_tag_compare_and_valid_check_port0_way2", + "CP3_1_tag_compare_and_valid_check_port0_way3", + "CP3_1_tag_compare_and_valid_check_port1_way0", + "CP3_1_tag_compare_and_valid_check_port1_way1", + "CP3_1_tag_compare_and_valid_check_port1_way2", + "CP3_1_tag_compare_and_valid_check_port1_way3", + "CP3_1_cache_miss_port0", + "CP3_1_cache_miss_port1", + "CP3_2_cache_hit_port0", + "CP3_2_cache_hit_port1", + ], + ) # ================================================================= # CP 4: PMP（物理内存保护）权限检查覆盖点 @@ -493,6 +574,24 @@ def define_iprefetchpipe_coverage(bundle, dut): }, name="CP4_PMP_Permission_Check" ) + g.mark_function( + "CP4_PMP_Permission_Check", + _M( + [ + "test_cp4_pmp_permission_check", + "test_pmp_interaction_apis", + "test_full_iprefetch_pipeline", + ] + ), + bin_name=[ + "CP4_1_access_allowed_port0", + "CP4_1_access_allowed_port1", + "CP4_2_access_forbidden_port0", + "CP4_2_access_forbidden_port1", + "CP4_3_mmio_access_port0", + "CP4_3_mmio_access_port1", + ], + ) # ================================================================= # CP 5: 异常处理和合并覆盖点 @@ -607,6 +706,28 @@ def define_iprefetchpipe_coverage(bundle, dut): }, name="CP5_Exception_Handling_And_Merging" ) + g.mark_function( + "CP5_Exception_Handling_And_Merging", + _M( + [ + "test_cp5_exception_handling_and_merging", + "test_itlb_interaction_apis", + "test_pmp_interaction_apis", + "test_dut_interface_internal_signals", + "test_full_iprefetch_pipeline", + ] + ), + bin_name=[ + "CP5_1_itlb_exception_only", + "CP5_2_pmp_exception_only", + "CP5_3_backend_exception_only", + "CP5_4_itlb_and_pmp_exception", + "CP5_5_itlb_and_backend_exception", + "CP5_6_pmp_and_backend_exception", + "CP5_7_all_exceptions", + "CP5_8_no_exception", + ], + ) # ================================================================= # CP 6: 发送请求到WayLookup模块覆盖点 @@ -646,6 +767,24 @@ def define_iprefetchpipe_coverage(bundle, dut): }, name="CP6_WayLookup_Request_Sending" ) + g.mark_function( + "CP6_WayLookup_Request_Sending", + _M( + [ + "test_cp6_send_request_to_waylookup", + "test_waylookup_interaction_apis", + "test_all_bundle_signals", + "test_full_iprefetch_pipeline", + ] + ), + bin_name=[ + "CP6_1_normal_send_to_waylookup", + "CP6_2_waylookup_not_ready", + "CP6_3_soft_prefetch_no_waylookup", + "CP6_1_waylookup_request_fired", + "CP6_1_hw_prefetch_with_s1_valid", + ], + ) # ================================================================= # CP 7: 状态机控制和请求处理流程覆盖点 @@ -724,6 +863,28 @@ def define_iprefetchpipe_coverage(bundle, dut): }, name="CP7_State_Machine_Control_And_Request_Processing" ) + g.mark_function( + "CP7_State_Machine_Control_And_Request_Processing", + _M( + [ + "test_cp7_state_machine_control_and_request_processing", + "test_status_query_apis", + "test_basic_control_apis", + "test_full_iprefetch_pipeline", + ] + ), + bin_name=[ + "CP7_1_1_idle_normal_flow", + "CP7_1_2_idle_to_itlb_resend", + "CP7_1_3_idle_to_enq_way", + "CP7_2_1_itlb_resend_to_enq_way", + "CP7_2_2_itlb_resend_to_meta_resend", + "CP7_3_meta_resend_to_enq_way", + "CP7_4_1_enq_way_to_idle", + "CP7_4_2_enq_way_to_enter_s2", + "CP7_5_enter_s2_to_idle", + ], + ) # ================================================================= # CP 8: 监控missUnit的请求覆盖点 @@ -818,6 +979,24 @@ def define_iprefetchpipe_coverage(bundle, dut): }, name="CP8_MissUnit_Monitoring" ) + g.mark_function( + "CP8_MissUnit_Monitoring", + _M( + [ + "test_cp8_monitor_missunit_requests", + "test_mshr_interaction_apis", + "test_full_iprefetch_pipeline", + ] + ), + bin_name=[ + "CP8_1_mshr_match_and_valid_port0", + "CP8_1_mshr_match_and_valid_port1", + "CP8_2_sram_hit_port0", + "CP8_2_sram_hit_port1", + "CP8_3_miss_mshr_and_sram_port0", + "CP8_3_miss_mshr_and_sram_port1", + ], + ) # ================================================================= # CP 9: 发送请求到missUnit覆盖点 @@ -853,10 +1032,11 @@ def define_iprefetchpipe_coverage(bundle, dut): "s2_MSHR_match_1": dut.GetInternalSignal(IPrefetchPipe_dict["s2_MSHR_match_1"], use_vpi=False), # 仲裁器相关信号 - "toMSHRArbiter_io_in_0_valid": dut.GetInternalSignal(IPrefetchPipe_dict["toMSHRArbiter_io_in_0_valid"], use_vpi=True), - "toMSHRArbiter_io_in_1_valid": dut.GetInternalSignal(IPrefetchPipe_dict["toMSHRArbiter_io_in_1_valid"], use_vpi=True), - "toMSHRArbiter_io_in_0_ready": dut.GetInternalSignal(IPrefetchPipe_dict["toMSHRArbiter_io_in_0_ready"], use_vpi=True), - "toMSHRArbiter_io_in_1_ready": dut.GetInternalSignal(IPrefetchPipe_dict["toMSHRArbiter_io_in_1_ready"], use_vpi=True), + "toMSHRArbiter_io_in_0_valid": dut.GetInternalSignal(IPrefetchPipe_dict["toMSHRArbiter_io_in_0_valid"], use_vpi=False), + "toMSHRArbiter_io_in_1_valid": dut.GetInternalSignal(IPrefetchPipe_dict["toMSHRArbiter_io_in_1_valid"], use_vpi=False), + # Some RTL variants optimize away this local ready wire; use MSHRReq.ready directly. + "toMSHRArbiter_io_in_0_ready": bundle.io._MSHRReq._ready, + "toMSHRArbiter_io_in_1_ready": dut.GetInternalSignal(IPrefetchPipe_dict["toMSHRArbiter_io_in_1_ready"], use_vpi=False), # bundle中的MSHR相关信号 "mshr_req_valid": bundle.io._MSHRReq._valid, @@ -989,6 +1169,35 @@ def define_iprefetchpipe_coverage(bundle, dut): }, name="CP9_Send_Request_To_MissUnit" ) + g.mark_function( + "CP9_Send_Request_To_MissUnit", + _M( + [ + "test_cp9_send_request_to_missunit", + "test_mshr_interaction_apis", + "test_dut_interface_internal_signals", + "test_all_bundle_signals", + "test_full_iprefetch_pipeline", + ] + ), + bin_name=[ + "CP9_1_1_miss_no_exception_send_port0", + "CP9_1_1_miss_no_exception_send_port1", + "CP9_1_2_sram_hit_no_send_port0", + "CP9_1_2_mshr_hit_no_send_port0", + "CP9_1_2_exception_no_send_port0", + "CP9_1_2_mmio_no_send_port0", + "CP9_1_3_doubleline_second_request", + "CP9_2_1_s1_real_fire_reset_has_send", + "CP9_2_2_request_sent_update_has_send_port0", + "CP9_2_2_request_sent_update_has_send_port1", + "CP9_2_3_avoid_duplicate_send_port0", + "CP9_2_3_avoid_duplicate_send_port1", + "CP9_2_4_correct_send_to_missunit_port0", + "CP9_2_4_correct_send_to_missunit_port1", + "CP9_2_5_arbiter_correct_arbitration", + ], + ) # ================================================================= # CP 10: 刷新机制覆盖点 @@ -1060,6 +1269,25 @@ def define_iprefetchpipe_coverage(bundle, dut): }, name="CP10_Flush_Mechanism" ) + g.mark_function( + "CP10_Flush_Mechanism", + _M( + [ + "test_cp10_flush_mechanism", + "test_smoke", + "test_basic_control_apis", + "test_status_query_apis", + "test_full_iprefetch_pipeline", + ] + ), + bin_name=[ + "CP10_1_global_flush", + "CP10_2_bpu_s0_flush", + "CP10_2_bpu_s1_flush", + "CP10_3_flush_state_reset", + "CP10_4_itlb_pipe_flush", + ], + ) return g @@ -1077,4 +1305,4 @@ def create_iprefetchpipe_coverage_groups(bundle, dut): """ iprefetchpipe_coverage = define_iprefetchpipe_coverage(bundle, dut) - return [iprefetchpipe_coverage] \ No newline at end of file + return [iprefetchpipe_coverage] diff --git a/ut_frontend/icache/iprefetchpipe/test/iprefetchpipe_fixture.py b/ut_frontend/icache/iprefetchpipe/test/iprefetchpipe_fixture.py index a89c9537..83d6855c 100644 --- a/ut_frontend/icache/iprefetchpipe/test/iprefetchpipe_fixture.py +++ b/ut_frontend/icache/iprefetchpipe/test/iprefetchpipe_fixture.py @@ -9,10 +9,11 @@ @toffee_test.fixture async def iprefetchpipe_env(toffee_request: toffee_test.ToffeeRequest): dut = toffee_request.create_dut(DUTIPrefetchPipe) + # Keep reset high before first clock activity to exercise reset init paths. + dut.reset.value = 1 dut.InitClock("clock") start_clock(dut) iprefetchpipe_env = IPrefetchPipeEnv(dut) - iprefetchpipe_env.dut.reset.value = 1 iprefetchpipe_env.dut.Step(10) iprefetchpipe_env.dut.reset.value = 0 iprefetchpipe_env.dut.Step(10) @@ -36,4 +37,4 @@ async def iprefetchpipe_env(toffee_request: toffee_test.ToffeeRequest): try: await task except asyncio.CancelledError: - break \ No newline at end of file + break diff --git a/ut_frontend/icache/iprefetchpipe/test/iprefetchpipe_test.py b/ut_frontend/icache/iprefetchpipe/test/iprefetchpipe_test.py index bff38b6f..bd7d98c4 100644 --- a/ut_frontend/icache/iprefetchpipe/test/iprefetchpipe_test.py +++ b/ut_frontend/icache/iprefetchpipe/test/iprefetchpipe_test.py @@ -7,12 +7,30 @@ # Helper function to access internal signals def get_internal_signal(env: IPrefetchPipeEnv, signal_path: str, vpi=False): - """Helper function to access internal DUT signals""" - if vpi is False: - signal = env.dut.GetInternalSignal(f"IPrefetchPipe_top.IPrefetchPipe.{signal_path}", use_vpi=False) + """Helper function to access internal DUT signals safely.""" + full_name = f"IPrefetchPipe_top.IPrefetchPipe.{signal_path}" + + # Cache exported internal signal names to avoid probing missing signals, + # which prints xsignal_cfg errors. + cache_name = "_iprefetchpipe_internal_signal_names_cache" + signal_names = getattr(env, cache_name, None) + if signal_names is None: + signal_names = set(env.dut.GetInternalSignalList(use_vpi=False)) + setattr(env, cache_name, signal_names) + + # Some signals are top-level IOs in the wrapper (not under .IPrefetchPipe) + alt_name = full_name.replace("IPrefetchPipe_top.IPrefetchPipe.io_", "IPrefetchPipe_top.io_") + query_name = None + if full_name in signal_names: + query_name = full_name + elif alt_name in signal_names: + query_name = alt_name else: - signal = env.dut.GetInternalSignal(f"IPrefetchPipe_top.IPrefetchPipe.{signal_path}", use_vpi=True) - return signal + return None + + if vpi is False: + return env.dut.GetInternalSignal(query_name, use_vpi=False) + return env.dut.GetInternalSignal(query_name, use_vpi=True) @toffee_test.testcase async def test_smoke(iprefetchpipe_env: IPrefetchPipeEnv): @@ -1721,6 +1739,19 @@ async def test_mshr_interaction_apis(iprefetchpipe_env: IPrefetchPipeEnv): bundle = iprefetchpipe_env.bundle errors = [] + + async def wait_internal_value(signal_name: str, expected: int, timeout_cycles: int = 8) -> bool: + """Wait until an internal signal reaches expected value within timeout cycles.""" + for _ in range(timeout_cycles): + sig = get_internal_signal(iprefetchpipe_env, signal_name) + if sig is not None and sig.value == expected: + return True + await bundle.step() + return False + + def read_internal_value(signal_name: str): + sig = get_internal_signal(iprefetchpipe_env, signal_name) + return None if sig is None else int(sig.value) try: # ==================== 测试类别1: 请求与MSHR匹配且有效 ==================== @@ -2067,13 +2098,113 @@ async def test_mshr_interaction_apis(iprefetchpipe_env: IPrefetchPipeEnv): except Exception as e: errors.append(f"类别4异常: {str(e)}") + + try: + # ==================== 测试类别5: MSHR更新分支与端口1 VS-NonLeaf覆盖 ==================== + toffee.info("=== 测试类别5: MSHR更新分支与端口1 VS-NonLeaf覆盖 ===") + async def prepare_doubleline_window(wait_doubleline: bool = True): + await agent.setup_environment(prefetch_enable=True) + # 阻塞WayLookup，保持请求停留在S1，便于覆盖s1_waymasks_r更新分支 + bundle.io._wayLookupWrite._ready.value = 0 + await bundle.step(1) + + paddr_0 = 0x1234B020 + paddr_1 = 0x1234B060 + start_addr = 0x8000B020 # 双行预取，请求端口1也有效 + next_addr = start_addr + 0x40 + + # 先稳定输入，再发请求，减少采样窗口竞争 + await agent.drive_itlb_response(port=0, paddr=paddr_0, miss=False, isForVSnonLeafPTE=False) + await agent.drive_itlb_response(port=1, paddr=paddr_1, miss=False, isForVSnonLeafPTE=True) + await agent.drive_meta_response(port=0, hit_ways=[True, False, False, False], target_paddr=paddr_0) + await agent.drive_meta_response(port=1, hit_ways=[False, False, True, False], target_paddr=paddr_1) + await agent.drive_pmp_response(port=0, mmio=False, instr_af=False) + await agent.drive_pmp_response(port=1, mmio=False, instr_af=False) + + req_result = await agent.drive_prefetch_request( + startAddr=start_addr, + isSoftPrefetch=False, + wait_for_ready=True, + timeout_cycles=10 + ) + assert req_result["send_success"] and req_result["doubleline"], f"双行请求发送失败: {req_result}" + if wait_doubleline: + assert await wait_internal_value("s1_doubleline", 1, timeout_cycles=6), \ + "双行请求应在6拍内进入s1_doubleline=1" + return start_addr, next_addr, paddr_0, paddr_1 + + # 子流程A: 覆盖端口1 VS-NonLeaf锁存、corrupt门控和new_info_way_same清零分支 + start_addr, next_addr, paddr_0, paddr_1 = await prepare_doubleline_window() + assert bundle.io._itlb._1._resp_bits._isForVSnonLeafPTE.value == 1, "port1 isForVSnonLeafPTE输入应为1" + assert read_internal_value("s1_req_paddr_reg_r_1") is not None, "内部信号s1_req_paddr_reg_r_1不可访问" + assert read_internal_value("s1_req_isForVSnonLeafPTE_tmp_r_1") is not None, "内部信号s1_req_isForVSnonLeafPTE_tmp_r_1不可访问" + assert await wait_internal_value("s1_req_paddr_reg_r_1", paddr_1, timeout_cycles=12), \ + f"s1_req_paddr_reg_r_1应在12拍内锁存port1 paddr，当前值=0x{read_internal_value('s1_req_paddr_reg_r_1'):x}" + assert await wait_internal_value("s1_req_isForVSnonLeafPTE_tmp_r_1", 1, timeout_cycles=12), \ + f"s1_req_isForVSnonLeafPTE_tmp_r_1应在12拍内锁存为1，当前值={read_internal_value('s1_req_isForVSnonLeafPTE_tmp_r_1')}" + + vset_0 = (start_addr >> 6) & 0xFF + vset_1 = (next_addr >> 6) & 0xFF + # 让blkPaddr[41:6]与请求ptag不相等，触发new_info_ptag_same=0路径 + mismatch_blkpaddr_0 = ((((paddr_0 >> 12) + 1) & ((1 << 36) - 1)) << 6) + mismatch_blkpaddr_1 = ((((paddr_1 >> 12) + 1) & ((1 << 36) - 1)) << 6) + + await agent.drive_mshr_response(corrupt=True, waymask=0xF, blkPaddr=mismatch_blkpaddr_0, vSetIdx=vset_0) + assert await wait_internal_value("_new_info_T", 0, timeout_cycles=6), \ + "corrupt=1时_new_info_T应保持为0" + await agent.drive_mshr_response(corrupt=False, waymask=0x1, blkPaddr=mismatch_blkpaddr_0, vSetIdx=vset_0) + assert await wait_internal_value("s1_waymasks_r_0", 0, timeout_cycles=8), \ + "new_info_way_same路径下s1_waymasks_r_0应清零" + await agent.drive_mshr_response(corrupt=False, waymask=0x4, blkPaddr=mismatch_blkpaddr_1, vSetIdx=vset_1) + assert await wait_internal_value("s1_waymasks_r_1", 0, timeout_cycles=8), \ + "new_info_way_same_1路径下s1_waymasks_r_1应清零" + await agent.deassert_prefetch_request() + await agent.clear_mshr_response() + bundle.io._wayLookupWrite._ready.value = 1 + await agent.drive_flush(flush_type="global") + await bundle.step(2) + + # 子流程B: 单独覆盖端口0 s1_SRAM_valid回退分支 + start_addr, _, paddr_0, _ = await prepare_doubleline_window(wait_doubleline=False) + vset_0 = (start_addr >> 6) & 0xFF + mismatch_blkpaddr_0 = ((((paddr_0 >> 12) + 1) & ((1 << 36) - 1)) << 6) + await agent.drive_mshr_response(corrupt=False, waymask=0x2, blkPaddr=mismatch_blkpaddr_0, vSetIdx=vset_0) + assert await wait_internal_value("s1_waymasks_r_0", 0x1, timeout_cycles=8), \ + "new_info_way_same为假时s1_waymasks_r_0应回退到SRAM waymask(0x1)" + await agent.deassert_prefetch_request() + await agent.clear_mshr_response() + bundle.io._wayLookupWrite._ready.value = 1 + await agent.drive_flush(flush_type="global") + await bundle.step(2) + + # 子流程C: 单独覆盖端口1 s1_SRAM_valid回退分支 + start_addr, next_addr, _, paddr_1 = await prepare_doubleline_window(wait_doubleline=False) + vset_1 = (next_addr >> 6) & 0xFF + mismatch_blkpaddr_1 = ((((paddr_1 >> 12) + 1) & ((1 << 36) - 1)) << 6) + await agent.drive_mshr_response(corrupt=False, waymask=0x1, blkPaddr=mismatch_blkpaddr_1, vSetIdx=vset_1) + assert await wait_internal_value("s1_waymasks_r_1", 0x4, timeout_cycles=8), \ + "new_info_way_same_1为假时s1_waymasks_r_1应回退到SRAM waymask(0x4)" + await agent.deassert_prefetch_request() + await agent.clear_mshr_response() + bundle.io._wayLookupWrite._ready.value = 1 + await agent.drive_flush(flush_type="global") + await bundle.step(2) + + toffee.info("✓ 类别5通过: MSHR关键分支/端口1 VS-NonLeaf 路径覆盖完成") + + except Exception as e: + await agent.clear_mshr_response() + bundle.io._wayLookupWrite._ready.value = 1 + bundle.io._req._valid.value = 0 + await bundle.step(3) + errors.append(f"类别5异常: {str(e)}") # 如果有错误，统一抛出 if errors: error_summary = f"test_mshr_interaction_apis发现{len(errors)}个错误:\n" + "\n".join(f" {i+1}. {err}" for i, err in enumerate(errors)) raise AssertionError(error_summary) - toffee.info(f"✓ test_mshr_interaction_apis: 所有4个测试类别均通过") + toffee.info(f"✓ test_mshr_interaction_apis: 所有5个测试类别均通过") @@ -7082,7 +7213,7 @@ async def test_cp8_monitor_missunit_requests(iprefetchpipe_env: IPrefetchPipeEnv def get_internal_signal(signal_name: str): """获取内部信号的辅助函数""" - return dut.GetInternalSignal(f"IPrefetchPipe_top.IPrefetchPipe.{signal_name}", use_vpi=False) + return globals()["get_internal_signal"](iprefetchpipe_env, signal_name, vpi=False) # ==================== CP8.1: 请求与MSHR匹配且有效 ==================== @@ -7713,7 +7844,13 @@ async def test_cp9_send_request_to_missunit(iprefetchpipe_env: IPrefetchPipeEnv) toffee.info("="*80) def get_internal_signal(signal_path: str): - return dut.GetInternalSignal(f"IPrefetchPipe_top.IPrefetchPipe.{signal_path}", use_vpi=False) + signal = globals()["get_internal_signal"](iprefetchpipe_env, signal_path, vpi=False) + if signal is not None: + return signal + # Some arbiter internals are optimized in this RTL variant. + if signal_path in ("_toMSHRArbiter_io_out_valid", "_toMSHRArbiter_io_in_0_ready"): + return bundle.io._MSHRReq._valid if signal_path.endswith("out_valid") else bundle.io._MSHRReq._ready + return signal # ==================== CP9.1.1: 请求未命中且无异常，需要发送到missUnit ==================== try: @@ -8503,8 +8640,10 @@ async def test_cp10_flush_mechanism(iprefetchpipe_env: IPrefetchPipeEnv): toffee.info(" 发送BPU S3刷新信号...") await agent.drive_flush( flush_type="bpu_s3", - ftq_flag=0, - ftq_value=30, + # Use non-zero flag to ensure io_flushFromBpu_s3_bits_flag is exercised. + ftq_flag=1, + # With current RTL expression precedence, pick value > req ftq value to trigger flush. + ftq_value=31, duration_cycles=1 ) @@ -8658,4 +8797,4 @@ async def test_cp10_flush_mechanism(iprefetchpipe_env: IPrefetchPipeEnv): toffee.info(" - CP10.2: 来自BPU的刷新信号验证 ✓") toffee.info(" - CP10.3: 刷新时状态机复位验证 ✓") toffee.info(" - CP10.4: ITLB管道同步刷新验证 ✓") - toffee.info("\nCP10: 刷新机制覆盖点测试全部通过!") \ No newline at end of file + toffee.info("\nCP10: 刷新机制覆盖点测试全部通过!")