platform: xuantie: Add custom PMU device for cycle/instret OF

Sscofpmf does not define overflow interrupts for the fixed cycle and
instret counters. XuanTie cores expose this via vendor mhpmevent0
(0x7E0) and mhpmevent2 (0x7E1), with the OF/INH bits split into
mhpmevent0H (0x7E2) / mhpmevent2H (0x7E3) on RV32 -- mirroring the
standard mhpmevent3/3H layout. mxstatus[8] (OFINT) is the per-hart
master gate that lets the vendor OF bit raise lcofip.

Instead of patching the generic sbi_pmu code path, register a
sbi_pmu_device (mirroring the thead c9xx pattern) and layer the
vendor OF handling on top of Sscofpmf via hw_counter_enable_irq /
hw_counter_disable_irq. The hooks only act on ctr_idx 0 and 2; the
programmable counters (ctr_idx >= 3) continue to use the standard
Sscofpmf code path unchanged. On RV32 the OF bit is reached via
mhpmevent0H/mhpmevent2H, matching what pmu_ctr_enable_irq_hw() does
for mhpmevent3H+.

Set mxstatus[8] (OFINT) in xuantie_early_init() outside the cold_boot
guard so it is enabled per hart on every boot path.

Wire it up via QUIRK_XUANTIE_PMU. The xuantie,dummy match enables it
alongside the existing quirks, and a new xuantie,pmu compatible is
provided for boards that need just this driver.

Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>

Author: cp0613

include/sbi/riscv_encoding.h

@@ -656,6 +656,9 @@
 #define CSR_MCOUNTINHIBIT		0x320
 #define CSR_MCYCLECFG			0x321
 #define CSR_MINSTRETCFG			0x322
+/* XuanTie vendor: per-counter event regs for fixed mcycle/minstret. */
+#define CSR_MHPMEVENT0			0x7E0
+#define CSR_MHPMEVENT2			0x7E1
 #define CSR_MHPMEVENT3			0x323
 #define CSR_MHPMEVENT4			0x324
 #define CSR_MHPMEVENT5			0x325
@@ -689,6 +692,9 @@
 /* For RV32 */
 #define CSR_MCYCLECFGH			0x721
 #define CSR_MINSTRETCFGH		0x722
+/* XuanTie vendor: high half of mhpmevent0/2 (for OF/INH bits on RV32). */
+#define CSR_MHPMEVENT0H			0x7E2
+#define CSR_MHPMEVENT2H			0x7E3
 #define CSR_MHPMEVENT3H			0x723
 #define CSR_MHPMEVENT4H			0x724
 #define CSR_MHPMEVENT5H			0x725

platform/generic/include/xuantie/xuantie_pmu.h

@@ -0,0 +1,23 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#ifndef __RISCV_XUANTIE_PMU_H__
+#define __RISCV_XUANTIE_PMU_H__
+
+/*
+ * XuanTie cores expose Sscofpmf-style OF semantics on the fixed cycle and
+ * instret counters via vendor per-counter event registers (mhpmevent0/2,
+ * and the matching high halves on RV32). The CSR addresses live in
+ * <sbi/riscv_encoding.h> next to the standard mhpmevent CSRs.
+ *
+ * mxstatus[8] (OFINT) is the per-hart master gate that lets the vendor
+ * OF bit raise lcofip; xuantie_pmu_enable_ofint() sets it.
+ */
+
+#define MXSTATUS_OFINT	BIT(8)
+
+void xuantie_pmu_register_device(void);
+void xuantie_pmu_enable_ofint(void);
+
+#endif /* __RISCV_XUANTIE_PMU_H__ */

platform/generic/include/xuantie/xuantie_quirk.h

@@ -8,6 +8,7 @@
 #define QUIRK_XUANTIE_PMC     BIT(0)
 #define QUIRK_XUANTIE_LINK    BIT(1)
 #define QUIRK_XUANTIE_PMP_EXT BIT(2)
+#define QUIRK_XUANTIE_PMU     BIT(3)
 
 struct xuantie_generic_quirks {
 	u32 quirk;

platform/generic/xuantie/objects.mk

@@ -3,4 +3,4 @@
 #
 
 carray-platform_override_modules-$(CONFIG_PLATFORM_XUANTIE) += xuantie_dummy
-platform-objs-$(CONFIG_PLATFORM_XUANTIE) += xuantie/xuantie_dummy.o xuantie/xuantie_pmc.o xuantie/xuantie_link.o xuantie/xuantie_pmp_ext.o
+platform-objs-$(CONFIG_PLATFORM_XUANTIE) += xuantie/xuantie_dummy.o xuantie/xuantie_pmc.o xuantie/xuantie_link.o xuantie/xuantie_pmp_ext.o xuantie/xuantie_pmu.o

platform/generic/xuantie/xuantie_dummy.c

@@ -14,6 +14,7 @@
 #include <xuantie/xuantie_pmc.h>
 #include <xuantie/xuantie_link.h>
 #include <xuantie/xuantie_pmp_ext.h>
+#include <xuantie/xuantie_pmu.h>
 
 static u32 gquirk = 0;
 
@@ -24,6 +25,10 @@ int xuantie_early_init(bool cold_boot)
 			xuantie_pmp_ext_cfg();
 	}
 
+	/* mxstatus[8] OFINT is per-hart: enable on every boot path. */
+	if (gquirk & QUIRK_XUANTIE_PMU)
+		xuantie_pmu_enable_ofint();
+
 	return generic_early_init(cold_boot);
 }
 
@@ -34,6 +39,8 @@ int xuantie_final_init(bool cold_boot)
 			xuantie_pmc_device_init();
 		if (gquirk & QUIRK_XUANTIE_LINK)
 			xuantie_link_pmu_device_init();
+		if (gquirk & QUIRK_XUANTIE_PMU)
+			xuantie_pmu_register_device();
 	}
 
 	return generic_final_init(cold_boot);
@@ -52,7 +59,8 @@ static int xuantie_dummy_platform_init(const void *fdt, int nodeoff,
 }
 
 static const struct xuantie_generic_quirks xuantie_quirks = {
-	.quirk = QUIRK_XUANTIE_PMC | QUIRK_XUANTIE_LINK | QUIRK_XUANTIE_PMP_EXT,
+	.quirk = QUIRK_XUANTIE_PMC | QUIRK_XUANTIE_LINK | QUIRK_XUANTIE_PMP_EXT |
+		 QUIRK_XUANTIE_PMU,
 };
 
 static const struct xuantie_generic_quirks xuantie_pmc_quirks = {
@@ -67,10 +75,15 @@ static const struct xuantie_generic_quirks xuantie_pmp_ext_quirks = {
 	.quirk = QUIRK_XUANTIE_PMP_EXT,
 };
 
+static const struct xuantie_generic_quirks xuantie_pmu_quirks = {
+	.quirk = QUIRK_XUANTIE_PMU,
+};
+
 static const struct fdt_match xuantie_dummy_match[] = {
 	{ .compatible = "xuantie,dummy", .data = &xuantie_quirks },
 	{ .compatible = "xuantie,pmc", .data = &xuantie_pmc_quirks },
 	{ .compatible = "xuantie,link", .data = &xuantie_link_quirks },
+	{ .compatible = "xuantie,pmu", .data = &xuantie_pmu_quirks },
 	{ .compatible = "riscv-virtio",  .data = &xuantie_pmp_ext_quirks }, // qemu debug
 	{ },
 };

platform/generic/xuantie/xuantie_pmu.c

@@ -0,0 +1,91 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_bitops.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_pmu.h>
+#include <thead/c9xx_encoding.h>
+#include <xuantie/xuantie_pmu.h>
+
+/*
+ * Sscofpmf does not provide OF interrupts for the fixed cycle/instret
+ * counters. XuanTie cores back those counters with vendor mhpmevent0/2
+ * CSRs whose top bits follow the same OF/MINH/...INH layout as the
+ * standard mhpmevent3+. The generic sbi_pmu_device hooks let us layer
+ * the vendor OF handling on top of the regular Sscofpmf path: the core
+ * already calls hw_counter_enable_irq/disable_irq with ctr_idx 0 and 2
+ * via the fixed-counter fallback in pmu_fixed_ctr_update_inhibit_bits().
+ *
+ * Only ctr_idx == 0 (cycle) and ctr_idx == 2 (instret) need vendor
+ * handling. Other counters are programmable mhpmevent3+ and follow the
+ * standard Sscofpmf code path unchanged.
+ */
+
+static void xuantie_pmu_ctr_enable_irq(uint32_t ctr_idx)
+{
+	if (ctr_idx != 0 && ctr_idx != 2)
+		return;
+
+	/*
+	 * Mirror pmu_ctr_enable_irq_hw(): only clear OF when no lcofip is
+	 * still pending, so we don't race with software that hasn't yet
+	 * handled the previous overflow.
+	 */
+	if (csr_read(CSR_MIP) & MIP_LCOFIP)
+		return;
+
+#if __riscv_xlen == 32
+	/* OF lives in the H half on RV32; clear via mhpmevent0H/mhpmevent2H. */
+	if (ctr_idx == 0)
+		csr_clear(CSR_MHPMEVENT0H, MHPMEVENTH_OF);
+	else
+		csr_clear(CSR_MHPMEVENT2H, MHPMEVENTH_OF);
+#else
+	if (ctr_idx == 0)
+		csr_clear(CSR_MHPMEVENT0, MHPMEVENT_OF);
+	else
+		csr_clear(CSR_MHPMEVENT2, MHPMEVENT_OF);
+#endif
+}
+
+static void xuantie_pmu_ctr_disable_irq(uint32_t ctr_idx)
+{
+	if (ctr_idx != 0 && ctr_idx != 2)
+		return;
+
+	/*
+	 * Setting OF latches the counter so a subsequent overflow cannot
+	 * raise lcofip until enable_irq clears it again. This matches the
+	 * "OF set = disabled" convention used by pmu_update_hw_mhpmevent().
+	 */
+#if __riscv_xlen == 32
+	if (ctr_idx == 0)
+		csr_set(CSR_MHPMEVENT0H, MHPMEVENTH_OF);
+	else
+		csr_set(CSR_MHPMEVENT2H, MHPMEVENTH_OF);
+#else
+	if (ctr_idx == 0)
+		csr_set(CSR_MHPMEVENT0, MHPMEVENT_OF);
+	else
+		csr_set(CSR_MHPMEVENT2, MHPMEVENT_OF);
+#endif
+}
+
+static const struct sbi_pmu_device xuantie_pmu_device = {
+	.name			= "xuantie,pmu",
+	.hw_counter_enable_irq	= xuantie_pmu_ctr_enable_irq,
+	.hw_counter_disable_irq	= xuantie_pmu_ctr_disable_irq,
+};
+
+void xuantie_pmu_register_device(void)
+{
+	sbi_pmu_set_device(&xuantie_pmu_device);
+}
+
+void xuantie_pmu_enable_ofint(void)
+{
+	csr_set(THEAD_C9XX_CSR_MXSTATUS, MXSTATUS_OFINT);
+}