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1. Delete the inaccurate event mapping PMU_HW_CACHE_REFERENCES, PMU_HW_CACHE_MISSES, DTLB_READ_MISS and ITLB_READ_MISS, because no CPU can provide them directly at present
2. Modify the inaccurate event mapping PMU_HW_BRANCH_INSTRUCTIONS and PMU_HW_BRANCH_MISSES, refer to C908
3. Modify the mask bitmap to 0x7fff8, because the CPU actually only supports 18 mhpmcounters
4. Fix BPU event value
5. The raw-event id mapping is optimized into one row, ranging from 0x0 to 0xff
Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
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The configuration of PMU can be referred to link:https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md[OpenSBI SBI PMU extension]
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The following is an example of PMU configuration for the Xuantie C-series CPU, which may need to be modified according to the datasheet during actual use.
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The following is an example of PMU configuration for the Xuantie C-series CPU written according to the datasheet.
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