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‎AppNotes/Digital_Up_Converter/dds.h‎

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//______________________________________________________________________________
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// dds.h:
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// - barebone direct digital synthesizer class
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//
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//
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// a. paek, sep 2016
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//______________________________________________________________________________
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/*
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* Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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* Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef DDS_H_
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#define DDS_H_

‎AppNotes/Digital_Up_Converter/duc.cpp‎

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/*
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* Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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* Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "duc.h"
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#if 1

‎AppNotes/Digital_Up_Converter/duc.h‎

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/*
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* Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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* Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef DUC_H
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#define DUC_H
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‎AppNotes/Digital_Up_Converter/duc_test.cpp‎

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/*
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* Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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* Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "duc.h"
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#include <math.h>
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‎AppNotes/Digital_Up_Converter/fir.h‎

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//______________________________________________________________________________
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// fir.h:
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// - various FIR module
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//
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//
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// a. paek, sep 2013
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//______________________________________________________________________________
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// some classes removed from xapp1299 reference code.
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/*
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* Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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* Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _FIR_H
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#define _FIR_H

‎Array/array_partition_block_cyclic/README‎

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matmul_partition_test.cpp
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run_hls.tcl
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run_vitis_commandline.sh
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run.py
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Running the Design using Vitis HLS (edit run_hls.tcl to set $hls_exec and enable specific run steps)
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=========================================================
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=====================================================
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./run_vitis_commandline.sh
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Running the design using python script
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=====================================================
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vitis -s run.py

‎Array/array_partition_block_cyclic/run.py‎

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import vitis
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import os
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cwd = os.getcwd()+'/'
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# Initialize session
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client = vitis.create_client()
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client.set_workspace(path='./w')
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# Delete the component if it already exists
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if os.path.exists('./w/array_partition_block_cyclic'):
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client.delete_component(name='array_partition_block_cyclic')
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# Create component. Create new config file in the component folder of the workspace
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comp = client.create_hls_component(name='array_partition_block_cyclic', cfg_file = ['hls_config.cfg'], template = 'empty_hls_component')
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# Get handle of config file, then programmatically set desired options
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cfg_file = client.get_config_file(path = './w/array_partition_block_cyclic/hls_config.cfg')
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cfg_file.set_value ( key = 'part', value = 'xcvu9p-flga2104-2-i')
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cfg_file.set_value (section = 'hls', key = 'syn.file', value = cwd+'matmul_partition.cpp')
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cfg_file.set_values(section = 'hls', key = 'tb.file', values = [cwd+'matmul_partition_test.cpp'])
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cfg_file.set_value (section = 'hls', key = 'syn.top', value = 'matmul_partition')
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cfg_file.set_value (section = 'hls', key = 'clock', value = '4') # 250MHz
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cfg_file.set_value (section = 'hls', key = 'flow_target', value = 'vivado')
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#cfg_file.set_value (section = 'hls', key = 'package.output.syn', value = '0')
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cfg_file.set_value (section = 'hls', key = 'package.output.format', value = 'rtl')
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cfg_file.set_value (section = 'hls', key = 'csim.code_analyzer', value = '0')
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# Run flow steps
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comp = client.get_component(name='array_partition_block_cyclic')
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comp.run(operation='C_SIMULATION')
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comp.run(operation='SYNTHESIS')
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comp.run(operation='CO_SIMULATION')

‎Array/array_partition_block_cyclic/run_hls.tcl‎

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#
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# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.

‎Array/array_partition_complete/README‎

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matmul_partition_test.cpp
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run_hls.tcl
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run_vitis_commandline.sh
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run.py
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Running the Design using Vitis HLS (edit run_hls.tcl to set $hls_exec and enable specific run steps)
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=========================================================
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=====================================================
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./run_vitis_commandline.sh
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Running the design using python script
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=====================================================
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vitis -s run.py
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‎Array/array_partition_complete/run.py‎

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import vitis
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import os
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cwd = os.getcwd()+'/'
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# Initialize session
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client = vitis.create_client()
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client.set_workspace(path='./w')
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# Delete the component if it already exists
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if os.path.exists('./w/array_partition_complete'):
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client.delete_component(name='array_partition_complete')
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# Create component. Create new config file in the component folder of the workspace
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comp = client.create_hls_component(name='array_partition_complete', cfg_file = ['hls_config.cfg'], template = 'empty_hls_component')
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# Get handle of config file, then programmatically set desired options
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cfg_file = client.get_config_file(path = './w/array_partition_complete/hls_config.cfg')
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cfg_file.set_value ( key = 'part', value = 'xcvu9p-flga2104-2-i')
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cfg_file.set_value (section = 'hls', key = 'syn.file', value = cwd+'matmul_partition.cpp')
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cfg_file.set_values(section = 'hls', key = 'tb.file', values = [cwd+'matmul_partition_test.cpp'])
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cfg_file.set_value (section = 'hls', key = 'syn.top', value = 'matmul_partition')
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cfg_file.set_value (section = 'hls', key = 'clock', value = '4') # 250MHz
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cfg_file.set_value (section = 'hls', key = 'flow_target', value = 'vitis')
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cfg_file.set_value (section = 'hls', key = 'package.output.syn', value = '0')
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cfg_file.set_value (section = 'hls', key = 'package.output.format', value = 'xo')
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cfg_file.set_value (section = 'hls', key = 'csim.code_analyzer', value = '0')
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# Run flow steps
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comp = client.get_component(name='array_partition_complete')
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comp.run(operation='C_SIMULATION')
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comp.run(operation='SYNTHESIS')
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comp.run(operation='CO_SIMULATION')

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