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Misc/rtl_as_blackbox/README

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This examaple uses the RTL blackbox feature.
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This example uses the RTL blackbox feature.
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The RTL blackbox enables the use of existing RTL IP in an HLS project. This lets you add RTL code to your C/C++ code for synthesis of the project by Vitis HLS.
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run.py
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Running the Design (edit x_hls.tcl to run synthesis)
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Running the Design (edit run_hls.tcl to run synthesis)
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=================================================
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vitis-run --mode hls --tcl run_hls.tcl
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README.md

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| Misc| Other examples such as the RTL blackbox flow and the LogiCore FFT from Vivado.|[fft](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Misc/fft)<br> [rtl_as_blackbox](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Misc/rtl_as_blackbox)|
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| Modelling| The essentials for loops, arbitrary precision types and vectors.|[basic_loops_primer](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Modeling/basic_loops_primer)<br> [using_arbitrary_precision_arith](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Modeling/using_arbitrary_precision_arith)<br> [using_vectors](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Modeling/using_vectors)<br> [using_array_stencil_1d](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Modeling/using_array_stencil_1d)|
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| Pipelining| Illustrating one of the most fundamental concept of HLS.|[hier_func](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Pipelining/Functions/hier_func)<br> [pipelined_loop](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Pipelining/Loops/pipelined_loop)|
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| Task_Level_Parallelism| Dataflow and free running streams with ```hls::task```.|[using_stream_of_blocks](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Task_level_Parallelism/Control_driven/Channels/using_stream_of_blocks)<br> [input_bypass](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Task_level_Parallelism/Control_driven/Patterns/input_bypass)<br> [unique_task_regions](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Task_level_Parallelism/Data_driven/unique_task_regions)|
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| Task_Level_Parallelism| Dataflow and free running streams with ```hls::task```.|[using_stream_of_blocks](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Task_level_Parallelism/Control_driven/Channels/using_stream_of_blocks)<br> [input_bypass](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Task_level_Parallelism/Control_driven/Patterns/input_bypass)<br> [unique_task_regions](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Task_level_Parallelism/Data_driven/unique_task_regions)<br>[using_directio_hs_in_tasks](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Task_level_Parallelism/Data_driven/using_directio_hs_in_tasks)|
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## Running the example scripts using Vitis Unified IDE
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{
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"name": "using_directio_in_hlsTasks",
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"description": "This example shows Direct I/O scalars with hls::task",
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"name": "using_directio_with_ap_hs_in_hlsTasks",
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"description": "This example shows Direct I/O ap_hs scalars with hls::task",
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"hls": {"config": "config.cfg"}
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}
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}

Task_level_Parallelism/Data_driven/using_directio_none_in_tasks/README.md renamed to Task_level_Parallelism/Data_driven/using_directio_none_in_tasks/README

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{
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"name": "using_directio_in_hlsTasks",
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"description": "This example shows Direct I/O scalars with hls::task",
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"name": "using_directio_with_ap_none_in_hlsTasks",
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"description": "This example shows Direct I/O ap_none scalars with hls::task",
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"hls": {"config": "config.cfg"}
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}
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}

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