IBERT_GTY

Versal™ Adaptive SoC Hardware Debug Tutorials See Vivado™ Development Environment on amd.com

Versal Adaptive SoC IBERT GTY Tutorial

Version: AMD Vivado™ 2023.2

Introduction

The AMD Versal™ adaptive SoC IBERT GTY is used to interact with GTY lanes contained in a design. It is used to debug and verify issues in high-speed serial I/O links. In contrast to previous architectures, Versal adaptive SoC IBERT GTY does not require additional IP and can be used with any design that utilizes the GTY transceivers. However, in some cases, it might be required to generate an IBERT capable design with minimal user interaction; this tutorial will demonstrate that flow.

In this tutorial, you will:

• Customize and generate an IBERT capable design using the IBERT Configurable Example Design (CED) in Vivado.
• Interact with the design in hardware using the Serial I/O Analyzer. This includes connecting to the target VCK190 evaluation board, programming the device, and interacting with the Serial I/O lanes.
• Perform a scan test to optimize a transceiver channel.

Hardware Setup

Required Hardware

• Versal AI Core Series VCK190 Evaluation Kit
• Micro USB Type C cable capable of connecting a PC to the VCK190 or a compatible programmer capable of programming the VCK190
• QSFP28 Loopback Connector (Recommended Part Number ML4002-28-C5) (Optional)

Board Setup

1. Setup the VCK190 as per XTP619 - VCK190 Software Install and Board Setup Tutorial.

   NOTE: Ensure that the VCK190 mode pins are setup for JTAG.

2. (Optional) Insert the QSFP28 loopback module into the QSFP cage (J288) on the VCK190.

Design Creation

A design that is IBERT capable can be generated quickly using the CED.

1. Launch Vivado 2023.2, and select Open Example Design at the landing page. Click Next to proceed.

2. In the Select Project Template window, scroll to the Versal IBERT template. Click Next.

   NOTE: If the Versal IBERT example design is not present, click Refresh.

   

3. (Optional) If desired, enter a project name, and choose a location for the project to be created.

4. This design targets the VCK190 Evaluation Kit which has the XCVC1902-2MSEVSVA2197 Versal AI Core device. In the part selection page, select: xcvc1902-vsva2197-2MP-e-S to target this part.

   NOTE: The Versal IBERT example design does not currently support selecting a board part.

   

5. Referencing the VCK190 User Guide GTY Transceivers Section and the VCK190 Evaluation Board User Guide Clock Generation Section, it can be observed that the following GTY Quads are connected as follows using the following reference clocks:

   Quad	Reference Clock Source	Reference Clock Frequency (MHz)
   200	Shared from QUAD 201	-
   201	SI570 Connected to REFCLK0 (GTY REFCLK X1Y2)	100 MHz
   204	SI570 Connected to REFCLK0 (GTY REFCLK X1Y8)	100 MHz

6. In the Design Preset menu, select the following, then click Next, and finally Finish to generate the design.

   

Generating the PDI and Programming into Hardware

1. After the IBERT Example Design is created, click Generate Device Image from the flow navigator.

   

Connecting to the VCK190 and Programming the PDI

1. When PDI generation is complete, click the option in the pop-up window to Open Hardware Manager.

   

2. Click the text, Open target, on the green banner to open a hardware target.

3. Click the Auto Connect option to connect to the locally connected VCK190.

   NOTE: If the target is not locally connected, see Vivado Design Suite User Guide: Programming and Debugging (UG908) for instructions to connect to a remote hardware target.

   

4. Click Program device on the green banner to program the generated PDI into the Versal device.

   

5. When the Program Device window appears, ensure that the PDI and Debug Probes File dialogs are each populated with a path to the respective files. Click Program.

   

6. When device programming completes, the IBERT core should be visible in the hardware panel:

   

Interacting with IBERT Using the Serial I/O Analyzer

1. The first step to interacting with IBERT is to create links, which allows you to link any TX and RX channel within the IBERT design. To start, click the Serial I/O Links tab, and select Create links.

   

2. In this design, each TX and RX channels will be linked together so all available links can be added by clicking the + button until all links are added.

   

3. Because Quads 201 and 204 do not have a physical loopback connector, select Internal Loopback for all channels in Quads 201 and 204. Quad 200 is connected to the external loopback connector and does not require internal loopback.

   NOTE: If a physical loopback connector is not inserted into J288, select Internal Loopback for all lanes.

   

4. After the links are created, they will be displayed in the Serial I/O Tabs. By default, IBERT will default to User Design for the TX and RX patterns, allowing user design data to be used. To bring the links up, change the TX and RX patterns for all links to PRBS 31 by clicking the TX and RX pattern drop down for Link Group 0.

   

5. Next, right-click Link 0, and select Create Scan.

   

6. For Horizontal Increment and Vertical Increment, select 2. Leave all other values default.

   

7. After the scan finishes, the Eye Diagram will be shown.

   

Chipscopy

ChipScoPy is an open-source project from AMD that enables high-level control of Versal debug cores (including IBERT) in Python without using Vivado. If you are interested in learning more, see ChipScoPy on GitHub. For an example that interacts with IBERT GTY lanes, see link_and_eye_scan.ipynb.

Conclusion

This tutorial has covered generating an IBERT capable design using the Versal IBERT CED, connecting to a VCK190 board, programming the programmable device image (PDI), setting up IBERT links, and running an eye-scan. To learn more about the Versal GTY transceivers, see Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002). To learn more about the programming and debug features in Vivado for Versal adaptive SoCs, see Vivado Design Suite User Guide: Programming and Debugging (UG908).

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