5555
5656import finn .transformation .fpgadataflow .convert_to_hw_layers as to_hw
5757import finn .transformation .streamline .absorb as absorb
58- from finn .analysis .fpgadataflow .dataflow_performance import dataflow_performance
58+ from finn .analysis .fpgadataflow .dataflow_performance import (
59+ dataflow_performance ,
60+ max_period ,
61+ )
5962from finn .analysis .fpgadataflow .exp_cycles_per_layer import exp_cycles_per_layer
6063from finn .analysis .fpgadataflow .hls_synth_res_estimation import hls_synth_res_estimation
6164from finn .analysis .fpgadataflow .op_and_param_counts import (
8285)
8386from finn .transformation .fpgadataflow .create_stitched_ip import CreateStitchedIP
8487from finn .transformation .fpgadataflow .derive_characteristic import (
85- DeriveCharacteristic ,
88+ DelayCharacteristicFunctions ,
8689 DeriveFIFOSizes ,
90+ DeriveTokenAccessVectors ,
91+ HandleBranches ,
92+ JustInTimeSynthesize ,
93+ LocalStretchCharacteristicFunctions ,
94+ ProducerDelayCharacteristicFunctions ,
8795)
8896from finn .transformation .fpgadataflow .hlssynth_ip import HLSSynthIP
8997from finn .transformation .fpgadataflow .insert_dwc import InsertDWC
104112)
105113from finn .transformation .fpgadataflow .set_exec_mode import SetExecMode
106114from finn .transformation .fpgadataflow .set_fifo_depths import (
115+ CapConvolutionFIFODepths ,
107116 InsertAndSetFIFODepths ,
108117 RemoveShallowFIFOs ,
109118 SplitLargeFIFOs ,
@@ -548,29 +557,92 @@ def step_set_fifo_depths(model: ModelWrapper, cfg: DataflowBuildConfig):
548557 """
549558
550559 if cfg .auto_fifo_depths :
551- if cfg .auto_fifo_strategy == "characterize" :
552- model = model .transform (InsertDWC ())
553- model = model .transform (SpecializeLayers (cfg ._resolve_fpga_part ()))
554- model = model .transform (GiveUniqueNodeNames ())
560+ model = model .transform (InsertDWC ())
561+ model = model .transform (SpecializeLayers (cfg ._resolve_fpga_part ()))
562+ model = model .transform (GiveUniqueNodeNames ())
563+ model = model .transform (AnnotateCycles ())
564+
565+ if cfg .auto_fifo_strategy == "analytical" :
566+ if cfg .just_in_time_synthesis :
567+ if cfg .tav_generation_strategy == "tree_model" :
568+ only_jit_nodes_without_tree = True
569+ else :
570+ only_jit_nodes_without_tree = False
571+ model = model .transform (
572+ JustInTimeSynthesize (
573+ cfg ._resolve_fpga_part (),
574+ cfg ._resolve_hls_clk_period (),
575+ only_jit_nodes_without_tree ,
576+ )
577+ )
578+ # model.save(f"{cfg.output_dir}/intermediate_models/step_rtl_generated_unsized.onnx")
579+
580+ period = int (model .analysis (dataflow_performance )["max_cycles" ])
555581 model = model .transform (
556- PrepareIP (cfg ._resolve_fpga_part (), cfg ._resolve_hls_clk_period ())
582+ DeriveTokenAccessVectors (
583+ model , period , cfg .tav_generation_strategy , cfg ._resolve_fpga_part (), 10.0
584+ )
585+ )
586+
587+ # model.save("rtlsim-derived_model.onnx")
588+
589+ period = int (model .analysis (dataflow_performance )["max_cycles" ])
590+ model = model .transform (
591+ LocalStretchCharacteristicFunctions (
592+ 1 ,
593+ period ,
594+ nodes_to_ignore = [],
595+ )
596+ )
597+
598+ period = int (model .analysis (dataflow_performance )["max_cycles" ])
599+
600+ model = model .transform (HandleBranches (model , period ))
601+
602+ period = int (model .analysis (dataflow_performance )["max_cycles" ])
603+ model = model .transform (
604+ DelayCharacteristicFunctions (
605+ 1 ,
606+ period ,
607+ nodes_to_ignore = [],
608+ )
609+ )
610+
611+ period = int (model .analysis (dataflow_performance )["max_cycles" ])
612+
613+ model = model .transform (
614+ ProducerDelayCharacteristicFunctions (
615+ 1 ,
616+ period ,
617+ nodes_to_ignore = [],
618+ )
619+ )
620+
621+ period = int (model .analysis (max_period )["max_cycles" ])
622+
623+ model = model .transform (
624+ DeriveFIFOSizes (
625+ period = period ,
626+ nodes_to_ignore = [],
627+ global_offset_correction = True ,
628+ tav_utilization_strategy = cfg .tav_utilization_strategy ,
629+ )
557630 )
558- model = model .transform (HLSSynthIP ())
559- model = model .transform (PrepareRTLSim ())
560- model = model .transform (AnnotateCycles ())
561- period = model .analysis (dataflow_performance )["max_cycles" ] + 10
562- model = model .transform (DeriveCharacteristic (period ))
563- model = model .transform (DeriveFIFOSizes ())
631+
564632 model = model .transform (
565633 InsertFIFO (
566634 vivado_ram_style = cfg .large_fifo_mem_style ,
567635 max_qsrl_depth = 256 ,
568636 create_shallow_fifos = True ,
569637 )
570638 )
639+
571640 model = model .transform (SpecializeLayers (cfg ._resolve_fpga_part ()))
572641 model = model .transform (GiveUniqueNodeNames ())
573642 model = model .transform (GiveReadableTensorNames ())
643+ if cfg .default_swg_exception :
644+ model = model .transform (CapConvolutionFIFODepths (max_qsrl_depth = 256 ))
645+
574646 elif cfg .auto_fifo_strategy == "largefifo_rtlsim" :
575647 if cfg .fifosim_save_waveform :
576648 report_dir = cfg .output_dir + "/report"
@@ -620,6 +692,7 @@ def step_set_fifo_depths(model: ModelWrapper, cfg: DataflowBuildConfig):
620692 "depth_trigger_uram" ,
621693 "depth_trigger_bram" ,
622694 ]
695+
623696 extract_model_config_to_json (model , cfg .output_dir + "/final_hw_config.json" , hw_attrs )
624697
625698 # perform FIFO splitting and shallow FIFO removal only after the final config
@@ -631,8 +704,9 @@ def step_set_fifo_depths(model: ModelWrapper, cfg: DataflowBuildConfig):
631704
632705 # after FIFOs are ready to go, call PrepareIP and HLSSynthIP again
633706 # this will only run for the new nodes (e.g. FIFOs and DWCs)
634- model = model .transform (PrepareIP (cfg ._resolve_fpga_part (), cfg ._resolve_hls_clk_period ()))
635- model = model .transform (HLSSynthIP ())
707+ # model = model.transform(PrepareIP(cfg._resolve_fpga_part(), cfg._resolve_hls_clk_period()))
708+ # model = model.transform(HLSSynthIP())
709+
636710 return model
637711
638712
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