Summary
Adds tiled matrix-vector activation support (TH > 1) for Versal DSP58, together with the MLO / FINNLoop external-memory weight-fetch path, and integrates both into the standard MVAU/FINNLoop test flows.

Key changes

• Tiled MVU RTL (finn-rtllib/mvu_tiled/): new cu_mvau_tiled, input_gen, acc_stage, weights_buff_tile, mvu_tiled_axi (+ wrapper and testbench). Replaces the earlier replay/transpose approach with an input_gen-based datapath.
• MLO weight fetch (finn-rtllib/fetch_weights/): reworked fetch_weights + local_weight_buffer, moved out of finn-rtllib/mlo/. External-memory weights packed per byte-aligned IWSIMD group using the memstream PE-flipped / TH-untiled ordering; per-SIMD byte
  alignment fixed for stitched-IP rtlsim.
• MVAU custom op (matrixvectoractivation.py, matrixvectoractivation_rtl.py, hwcustomop.py): TH-aware folding, memstream depth scaling with TH, DSP58 double-pumped compute wiring, and HLS interface updates. Obsolete MMAU/ram_p_c files removed (tiled MMAU RTL kept under mvu_tiled/ for future use).
• Loop rolling / FIFO sizing: MLO external_mem is now set by loop rolling rather than the user; FINNLoop m_axi weight ports associated by MVAU name; set_fifo_depths updates for the loop/MLO flow.
• Tests: tiled MatMul + MLO variants folded into test_fpgadataflow_mvau.py, test_fpgadataflow_finnloop.py, and test_loop_rolling.py; guards added for unsupported configs (tiling + double-pumping disallowed; SIMD==1 + pumpedCompute disallowed).

Notes

• Tiling (TH > 1) and clock double-pumping are mutually exclusive by design and skipped in tests.
• Depends on the XSI double-pumped stimulus-timing fix (separate PR) for the pumpedCompute rtlsim path.