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2 parents 5363e38 + c5349c4 commit b44763bCopy full SHA for b44763b
1 file changed
rtl/pll/pll_0002.v
@@ -25,7 +25,7 @@ module pll_0002(
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.output_clock_frequency0("100.000000 MHz"),
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.phase_shift0("0 ps"),
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.duty_cycle0(50),
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- .output_clock_frequency1("27.000000 MHz"),
+ .output_clock_frequency1("27027027 Hz"),
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.phase_shift1("0 ps"),
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.duty_cycle1(50),
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.output_clock_frequency2("0 MHz"),
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