Fix output clock frequency in pll_0002 module

Author: asturur

rtl/pll/pll_0002.v

@@ -25,7 +25,7 @@ module  pll_0002(
 		.output_clock_frequency0("100.000000 MHz"),
 		.phase_shift0("0 ps"),
 		.duty_cycle0(50),
-		.output_clock_frequency1("27.000000 MHz"),
+		.output_clock_frequency1("27027027 Hz"),
 		.phase_shift1("0 ps"),
 		.duty_cycle1(50),
 		.output_clock_frequency2("0 MHz"),