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Check that stm32 code is up to date (#330)
* Check that stm32 code is up to date * Add working directory * fix typo * try building regz in release safe mode * don't fail PR on check failure (might want to follow up with another PR)
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.github/workflows/ci.yml

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@@ -156,3 +156,27 @@ jobs:
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run: zig build -Doptimize=ReleaseSmall --summary all
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working-directory: examples/${{ matrix.example_dir }}
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stm32-gen-check:
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name: Check that stm32 generated code is up to date
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continue-on-error: true
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runs-on: ubuntu-latest
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steps:
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- name: Checkout code
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uses: actions/checkout@v3
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- name: Setup Zig
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uses: mlugg/setup-zig@v1
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with:
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version: ${{ env.ZIG_VERSION }}
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- name: Generate Code
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run: zig build update
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working-directory: port/stmicro/stm32
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- name: Check for code diffs
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run: |
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if [[ $(git status --porcelain) ]]; then
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echo "Code differences detected:"
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git diff
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echo "Please commit or fix these changes to proceed."
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exit 1
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else
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echo "No code differences detected."
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fi

build.zig

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@@ -328,7 +328,7 @@ pub fn MicroBuild(port_select: PortSelect) type {
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cpu_mod.addImport("microzig", core_mod);
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core_mod.addImport("cpu", cpu_mod);
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const regz_exe = b.dependency("tools/regz", .{}).artifact("regz");
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const regz_exe = b.dependency("tools/regz", .{ .optimize = .ReleaseSafe }).artifact("regz");
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const chip_source = switch (target.chip.register_definition) {
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.atdf, .svd => |file| blk: {
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const regz_run = b.addRunArtifact(regz_exe);

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