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1 | 1 | const std = @import("std"); |
2 | | -const MicroZig = @import("microzig/build"); |
| 2 | +const microzig = @import("microzig/build-internals"); |
3 | 3 |
|
4 | | -fn path(comptime suffix: []const u8) std.Build.LazyPath { |
5 | | - return .{ |
6 | | - .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix), |
7 | | - }; |
8 | | -} |
| 4 | +const Self = @This(); |
| 5 | + |
| 6 | +chips: struct { |
| 7 | + esp32_c3: *const microzig.Target, |
| 8 | +}, |
9 | 9 |
|
10 | | -const esp_riscv = .{ |
11 | | - .name = "Espressif RISC-V", |
12 | | - .root_source_file = path("/src/cpus/espressif-riscv.zig"), |
13 | | - .target = std.Target.Query{ |
14 | | - .cpu_arch = .riscv32, |
15 | | - .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 }, |
16 | | - .cpu_features_add = std.Target.riscv.featureSet(&.{ |
17 | | - std.Target.riscv.Feature.c, |
18 | | - std.Target.riscv.Feature.m, |
19 | | - }), |
20 | | - .os_tag = .freestanding, |
21 | | - .abi = .eabi, |
22 | | - }, |
23 | | -}; |
24 | | - |
25 | | -const hal = .{ |
26 | | - .root_source_file = path("/src/hals/ESP32_C3.zig"), |
27 | | -}; |
28 | | - |
29 | | -pub const chips = struct { |
30 | | - pub const esp32_c3 = MicroZig.Target{ |
31 | | - .preferred_format = .bin, // TODO: Exchange FLAT format with .esp format |
| 10 | +boards: struct {}, |
| 11 | + |
| 12 | +pub fn init(dep: *std.Build.Dependency) Self { |
| 13 | + const b = dep.builder; |
| 14 | + |
| 15 | + const hal: microzig.HardwareAbstractionLayer = .{ |
| 16 | + .root_source_file = b.path("src/hals/ESP32_C3.zig"), |
| 17 | + }; |
| 18 | + const chip_esp32c3: microzig.Target = .{ |
| 19 | + .dep = dep, |
| 20 | + // TODO: Exchange FLAT format with .esp format |
| 21 | + .preferred_binary_format = .bin, |
32 | 22 | .chip = .{ |
33 | 23 | .name = "ESP32-C3", |
34 | 24 | .url = "https://www.espressif.com/en/products/socs/esp32-c3", |
35 | | - |
36 | | - .cpu = esp_riscv, |
37 | | - |
38 | | - .register_definition = .{ |
39 | | - .svd = path("/src/chips/ESP32-C3.svd"), |
| 25 | + .cpu = std.Target.Query{ |
| 26 | + .cpu_arch = .riscv32, |
| 27 | + .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 }, |
| 28 | + .cpu_features_add = std.Target.riscv.featureSet(&.{ |
| 29 | + std.Target.riscv.Feature.c, |
| 30 | + std.Target.riscv.Feature.m, |
| 31 | + }), |
| 32 | + .os_tag = .freestanding, |
| 33 | + .abi = .eabi, |
40 | 34 | }, |
41 | | - |
| 35 | + .cpu_module_file = b.path("src/cpus/espressif-riscv.zig"), |
| 36 | + .register_definition = .{ .svd = b.path("src/chips/ESP32-C3.svd") }, |
42 | 37 | .memory_regions = &.{ |
43 | | - .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus |
44 | | - .{ .kind = .ram, .offset = 0x3FC8_0000, .length = 0x0006_0000 }, // sram 1, data bus |
| 38 | + // external memory, ibus |
| 39 | + .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, |
| 40 | + // sram 1, data bus |
| 41 | + .{ .kind = .ram, .offset = 0x3FC8_0000, .length = 0x0006_0000 }, |
45 | 42 | }, |
46 | 43 | }, |
47 | 44 | .hal = hal, |
48 | 45 | }; |
49 | | -}; |
50 | 46 |
|
51 | | -pub const boards = struct {}; |
| 47 | + return .{ |
| 48 | + .chips = .{ |
| 49 | + .esp32_c3 = chip_esp32c3.derive(.{}), |
| 50 | + }, |
| 51 | + .boards = .{}, |
| 52 | + }; |
| 53 | +} |
52 | 54 |
|
53 | 55 | pub fn build(b: *std.Build) void { |
54 | | - _ = b.step("test", "Run platform agnostic unit tests"); |
| 56 | + const optimize = b.standardOptimizeOption(.{}); |
| 57 | + |
| 58 | + const unit_tests = b.addTest(.{ |
| 59 | + .root_source_file = b.path("src/hal.zig"), |
| 60 | + .optimize = optimize, |
| 61 | + }); |
| 62 | + |
| 63 | + const unit_tests_run = b.addRunArtifact(unit_tests); |
| 64 | + const test_step = b.step("test", "Run platform agnostic unit tests"); |
| 65 | + test_step.dependOn(&unit_tests_run.step); |
55 | 66 | } |
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