Interfacing to Xilinx Vivado block design environment#26

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motylewski wants to merge 16 commits into

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Commits on Mar 27, 2020

fix aximrd2wbsp.v parameters AW. fix S_AXI_ARREADY output wire
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Commits on Jul 21, 2020

ported wb2axip to Xilinx Vivado Verilog (not SystemVerilog because import in block design does not work in 2019.2) replaced localparam, removed default_nettype none
motylewski
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Commits on Jul 27, 2020

fixed default_nettype in all wb2axip modules
motylewski
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Commits on Jul 28, 2020

added X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM CYC" to module axim2wbsp
motylewski
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Commits on Aug 1, 2020

added X_INTERFACE_INFOattributes for automatic AXI bus detection in Vivado
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Commits on Aug 6, 2020

added ifndef YOSYS default_wiretype to 2 files
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Commits on Aug 7, 2020

Commits on Aug 10, 2020

pulling from upstream ZipCPU
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Commits on Aug 11, 2020

Commits on Aug 13, 2020

Commits on Aug 17, 2020