create_stm32f1_project

#!/bin/sh

if [ "$1" = "--help" ]
  then
      echo ""
      echo "    STM32F1 Project Creator v0.05";
      echo "wget, st-utility and GNU Arm Embedded Toolchain are required"
      echo
      echo "Usage:"
      echo "        $0 [command] [command] ... [options] [options] ... "
      echo
      echo "Commands:"
      echo "        mdk  generate simple Keil MDK-ARM config"
      echo "        pdf  fetch stm32f10x datasheet and reference manual (rm0008)"
      echo "        opt  perform more optimizations"               
      exit
fi


wg="wget -c"
raw=https://raw.githubusercontent.com
st=$raw/STMicroelectronics/
cmsis=$st/STM32CubeF1/master/Drivers/CMSIS/Include
f1=$st/cmsis_device_f1/master
svd="https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/refs/heads/main/data/STMicro/STM32F103xx.svd"

$wg $cmsis/cmsis_compiler.h $cmsis/cmsis_gcc.h $cmsis/cmsis_version.h $cmsis/core_cm3.h \
    $f1/Include/stm32f1xx.h $f1/Include/stm32f103xb.h $f1/Include/system_stm32f1xx.h $f1/Source/Templates/system_stm32f1xx.c \
    $f1/Source/Templates/gcc/startup_stm32f103xb.s $f1/Source/Templates/gcc/linker/STM32F103XB_FLASH.ld $svd

for arg in "$@"; do
    if [ "$arg" = "pdf" ]; then
        $wg "https://web.archive.org/web/20240717135940/https://www.st.com/resource/en/reference_manual/rm0008-stm32f101xx-stm32f102xx-stm32f103xx-stm32f105xx-and-stm32f107xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf" -O rm0008.pdf
        $wg "https://web.archive.org/web/20241004133110/https://www.st.com/resource/en/datasheet/stm32f103c8.pdf"
        break
    fi
done

for arg in "$@"; do
    if [ "$arg" = "mdk" ]; then
        $wg $cmsis/cmsis_armclang.h
        mkdir MDK-ARM
        cd MDK-ARM
        $wg $f1/Source/Templates/arm/startup_stm32f103xb.s
        def_set1="<Define>STM32F103xB,"
        def_set2="USE_HSE=0, USE_PLL=0, USE_USART=1, USE_I2C=0, USE_SPI=0, USE_RTC=0, USE_LSE=0, USE_BTN=0, USE_TIM2=0, USE_CRC=0, USE_ADC=0, USE_FLASH=0, USE_IWDG=0, USE_WWDG=0, USE_EXTI=0, USE_RNG=0</Define>"
        cat << MDK_CONFIG > project.uvprojx
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
  <SchemaVersion>2.1</SchemaVersion>
  <Header>### uVision Project, (C) Keil Software</Header>
  <Targets>
    <Target>
      <TargetName>Debug</TargetName>
      <ToolsetNumber>0x4</ToolsetNumber>
      <ToolsetName>ARM-ADS</ToolsetName>
      <pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
      <uAC6>1</uAC6>
      <TargetOption>
        <TargetCommonOption>
          <Device>STM32F103CB</Device>
          <Vendor>STMicroelectronics</Vendor>
          <PackID>Keil.STM32F1xx_DFP.2.4.0</PackID>
          <PackURL>http://www.keil.com/pack/</PackURL>
          <Cpu>IRAM(0x20000000,0x00005000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M3") CLOCK(8000000) ELITTLE</Cpu>
          <FlashUtilSpec></FlashUtilSpec>
          <StartupFile></StartupFile>
          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0(195Device:STM32F103CB\STM32F10x_128.FLM))</FlashDriverDll>
          <DeviceId>0</DeviceId>
          <RegisterFile>195Device:STM32F103CB\Include\stm32f10x.h</RegisterFile>
          <MemoryEnv></MemoryEnv>
          <Cmp></Cmp>
          <Asm></Asm>
          <Linker></Linker>
          <OHString></OHString>
          <InfinionOptionDll></InfinionOptionDll>
          <SLE66CMisc></SLE66CMisc>
          <SLE66AMisc></SLE66AMisc>
          <SLE66LinkerMisc></SLE66LinkerMisc>
          <SFDFile>195Device:STM32F103CB\STM32F103xx.svd</SFDFile>
          <bCustSvd>0</bCustSvd>
          <UseEnv>0</UseEnv>
          <BinPath></BinPath>
          <IncludePath></IncludePath>
          <LibPath></LibPath>
          <RegisterFilePath></RegisterFilePath>
          <DBRegisterFilePath></DBRegisterFilePath>
          <TargetStatus>
            <Error>0</Error>
            <ExitCodeStop>0</ExitCodeStop>
            <ButtonStop>0</ButtonStop>
            <NotGenerated>0</NotGenerated>
            <InvalidFlash>1</InvalidFlash>
          </TargetStatus>
          <OutputDirectory>.\OUTPUT\</OutputDirectory>
          <OutputName>project</OutputName>
          <CreateExecutable>1</CreateExecutable>
          <CreateLib>0</CreateLib>
          <CreateHexFile>1</CreateHexFile>
          <DebugInformation>1</DebugInformation>
          <BrowseInformation>1</BrowseInformation>
          <ListingPath></ListingPath>
          <HexFormatSelection>1</HexFormatSelection>
          <Merge32K>0</Merge32K>
          <CreateBatchFile>0</CreateBatchFile>
          <BeforeCompile>
            <RunUserProg1>0</RunUserProg1>
            <RunUserProg2>0</RunUserProg2>
            <UserProg1Name></UserProg1Name>
            <UserProg2Name></UserProg2Name>
            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
            <nStopU1X>0</nStopU1X>
            <nStopU2X>0</nStopU2X>
          </BeforeCompile>
          <BeforeMake>
            <RunUserProg1>0</RunUserProg1>
            <RunUserProg2>0</RunUserProg2>
            <UserProg1Name></UserProg1Name>
            <UserProg2Name></UserProg2Name>
            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
            <nStopB1X>0</nStopB1X>
            <nStopB2X>0</nStopB2X>
          </BeforeMake>
          <AfterMake>
            <RunUserProg1>0</RunUserProg1>
            <RunUserProg2>0</RunUserProg2>
            <UserProg1Name></UserProg1Name>
            <UserProg2Name></UserProg2Name>
            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
            <nStopA1X>0</nStopA1X>
            <nStopA2X>0</nStopA2X>
          </AfterMake>
          <SelectedForBatchBuild>1</SelectedForBatchBuild>
          <SVCSIdString></SVCSIdString>
        </TargetCommonOption>
        <CommonProperty>
          <UseCPPCompiler>0</UseCPPCompiler>
          <RVCTCodeConst>0</RVCTCodeConst>
          <RVCTZI>0</RVCTZI>
          <RVCTOtherData>0</RVCTOtherData>
          <ModuleSelection>0</ModuleSelection>
          <IncludeInBuild>1</IncludeInBuild>
          <AlwaysBuild>0</AlwaysBuild>
          <GenerateAssemblyFile>0</GenerateAssemblyFile>
          <AssembleAssemblyFile>0</AssembleAssemblyFile>
          <PublicsOnly>0</PublicsOnly>
          <StopOnExitCode>3</StopOnExitCode>
          <CustomArgument></CustomArgument>
          <IncludeLibraryModules></IncludeLibraryModules>
          <ComprImg>0</ComprImg>
        </CommonProperty>
        <DllOption>
          <SimDllName>SARMCM3.DLL</SimDllName>
          <SimDllArguments> -REMAP</SimDllArguments>
          <SimDlgDll>DCM.DLL</SimDlgDll>
          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
          <TargetDllName>SARMCM3.DLL</TargetDllName>
          <TargetDllArguments></TargetDllArguments>
          <TargetDlgDll>TCM.DLL</TargetDlgDll>
          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
        </DllOption>
        <DebugOption>
          <OPTHX>
            <HexSelection>1</HexSelection>
            <HexRangeLowAddress>0</HexRangeLowAddress>
            <HexRangeHighAddress>0</HexRangeHighAddress>
            <HexOffset>0</HexOffset>
            <Oh166RecLen>16</Oh166RecLen>
          </OPTHX>
        </DebugOption>
        <Utilities>
          <Flash1>
            <UseTargetDll>1</UseTargetDll>
            <UseExternalTool>0</UseExternalTool>
            <RunIndependent>0</RunIndependent>
            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
            <Capability>1</Capability>
            <DriverSelection>4101</DriverSelection>
          </Flash1>
          <bUseTDR>1</bUseTDR>
          <Flash2>BIN\UL2CM3.DLL</Flash2>
          <Flash3></Flash3>
          <Flash4></Flash4>
          <pFcarmOut></pFcarmOut>
          <pFcarmGrp></pFcarmGrp>
          <pFcArmRoot></pFcArmRoot>
          <FcArmLst>0</FcArmLst>
        </Utilities>
        <TargetArmAds>
          <ArmAdsMisc>
            <GenerateListings>0</GenerateListings>
            <asHll>1</asHll>
            <asAsm>1</asAsm>
            <asMacX>1</asMacX>
            <asSyms>1</asSyms>
            <asFals>1</asFals>
            <asDbgD>1</asDbgD>
            <asForm>1</asForm>
            <ldLst>0</ldLst>
            <ldmm>1</ldmm>
            <ldXref>1</ldXref>
            <BigEnd>0</BigEnd>
            <AdsALst>1</AdsALst>
            <AdsACrf>1</AdsACrf>
            <AdsANop>0</AdsANop>
            <AdsANot>0</AdsANot>
            <AdsLLst>1</AdsLLst>
            <AdsLmap>1</AdsLmap>
            <AdsLcgr>1</AdsLcgr>
            <AdsLsym>1</AdsLsym>
            <AdsLszi>1</AdsLszi>
            <AdsLtoi>1</AdsLtoi>
            <AdsLsun>1</AdsLsun>
            <AdsLven>1</AdsLven>
            <AdsLsxf>1</AdsLsxf>
            <RvctClst>0</RvctClst>
            <GenPPlst>0</GenPPlst>
            <AdsCpuType>"Cortex-M3"</AdsCpuType>
            <RvctDeviceName></RvctDeviceName>
            <mOS>0</mOS>
            <uocRom>0</uocRom>
            <uocRam>0</uocRam>
            <hadIROM>1</hadIROM>
            <hadIRAM>1</hadIRAM>
            <hadXRAM>0</hadXRAM>
            <uocXRam>0</uocXRam>
            <RvdsVP>0</RvdsVP>
            <RvdsMve>0</RvdsMve>
            <RvdsCdeCp>0</RvdsCdeCp>
            <hadIRAM2>0</hadIRAM2>
            <hadIROM2>0</hadIROM2>
            <StupSel>8</StupSel>
            <useUlib>1</useUlib>
            <EndSel>0</EndSel>
            <uLtcg>0</uLtcg>
            <nSecure>0</nSecure>
            <RoSelD>3</RoSelD>
            <RwSelD>3</RwSelD>
            <CodeSel>0</CodeSel>
            <OptFeed>0</OptFeed>
            <NoZi1>0</NoZi1>
            <NoZi2>0</NoZi2>
            <NoZi3>0</NoZi3>
            <NoZi4>0</NoZi4>
            <NoZi5>0</NoZi5>
            <Ro1Chk>0</Ro1Chk>
            <Ro2Chk>0</Ro2Chk>
            <Ro3Chk>0</Ro3Chk>
            <Ir1Chk>1</Ir1Chk>
            <Ir2Chk>0</Ir2Chk>
            <Ra1Chk>0</Ra1Chk>
            <Ra2Chk>0</Ra2Chk>
            <Ra3Chk>0</Ra3Chk>
            <Im1Chk>1</Im1Chk>
            <Im2Chk>0</Im2Chk>
            <OnChipMemories>
              <Ocm1>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </Ocm1>
              <Ocm2>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </Ocm2>
              <Ocm3>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </Ocm3>
              <Ocm4>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </Ocm4>
              <Ocm5>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </Ocm5>
              <Ocm6>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </Ocm6>
              <IRAM>
                <Type>0</Type>
                <StartAddress>0x20000000</StartAddress>
                <Size>0x5000</Size>
              </IRAM>
              <IROM>
                <Type>1</Type>
                <StartAddress>0x8000000</StartAddress>
                <Size>0x20000</Size>
              </IROM>
              <XRAM>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </XRAM>
              <OCR_RVCT1>
                <Type>1</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </OCR_RVCT1>
              <OCR_RVCT2>
                <Type>1</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </OCR_RVCT2>
              <OCR_RVCT3>
                <Type>1</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </OCR_RVCT3>
              <OCR_RVCT4>
                <Type>1</Type>
                <StartAddress>0x8000000</StartAddress>
                <Size>0x20000</Size>
              </OCR_RVCT4>
              <OCR_RVCT5>
                <Type>1</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </OCR_RVCT5>
              <OCR_RVCT6>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </OCR_RVCT6>
              <OCR_RVCT7>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </OCR_RVCT7>
              <OCR_RVCT8>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </OCR_RVCT8>
              <OCR_RVCT9>
                <Type>0</Type>
                <StartAddress>0x20000000</StartAddress>
                <Size>0x5000</Size>
              </OCR_RVCT9>
              <OCR_RVCT10>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </OCR_RVCT10>
            </OnChipMemories>
            <RvctStartVector></RvctStartVector>
          </ArmAdsMisc>
          <Cads>
            <interw>1</interw>
            <Optim>1</Optim>
            <oTime>0</oTime>
            <SplitLS>0</SplitLS>
            <OneElfS>1</OneElfS>
            <Strict>0</Strict>
            <EnumInt>0</EnumInt>
            <PlainCh>0</PlainCh>
            <Ropi>0</Ropi>
            <Rwpi>0</Rwpi>
            <wLevel>2</wLevel>
            <uThumb>0</uThumb>
            <uSurpInc>0</uSurpInc>
            <uC99>1</uC99>
            <uGnu>0</uGnu>
            <useXO>0</useXO>
            <v6Lang>6</v6Lang>
            <v6LangP>9</v6LangP>
            <vShortEn>1</vShortEn>
            <vShortWch>1</vShortWch>
            <v6Lto>0</v6Lto>
            <v6WtE>1</v6WtE>
            <v6Rtti>0</v6Rtti>
            <VariousControls>
              <MiscControls>-Wno-missing-prototypes -Wno-unreachable-code-return</MiscControls>
              $def_set1 USE_SWD=1, $def_set2
              <Undefine></Undefine>
              <IncludePath>..</IncludePath>
            </VariousControls>
          </Cads>
          <Aads>
            <interw>1</interw>
            <Ropi>0</Ropi>
            <Rwpi>0</Rwpi>
            <thumb>0</thumb>
            <SplitLS>0</SplitLS>
            <SwStkChk>0</SwStkChk>
            <NoWarn>0</NoWarn>
            <uSurpInc>0</uSurpInc>
            <useXO>0</useXO>
            <ClangAsOpt>4</ClangAsOpt>
            <VariousControls>
              <MiscControls></MiscControls>
              <Define></Define>
              <Undefine></Undefine>
              <IncludePath></IncludePath>
            </VariousControls>
          </Aads>
          <LDads>
            <umfTarg>1</umfTarg>
            <Ropi>0</Ropi>
            <Rwpi>0</Rwpi>
            <noStLib>0</noStLib>
            <RepFail>1</RepFail>
            <useFile>0</useFile>
            <TextAddressRange></TextAddressRange>
            <DataAddressRange></DataAddressRange>
            <pXoBase></pXoBase>
            <ScatterFile></ScatterFile>
            <IncludeLibs></IncludeLibs>
            <IncludeLibsPath></IncludeLibsPath>
            <Misc></Misc>
            <LinkerInputFile></LinkerInputFile>
            <DisabledWarnings></DisabledWarnings>
          </LDads>
        </TargetArmAds>
      </TargetOption>
      <Groups>
        <Group>
          <GroupName>startup</GroupName>
          <Files>
            <File>
              <FileName>startup_stm32f103xb.s</FileName>
              <FileType>2</FileType>
              <FilePath>startup_stm32f103xb.s</FilePath>
            </File>
            <File>
              <FileName>system_stm32f1xx.c</FileName>
              <FileType>1</FileType>
              <FilePath>../system_stm32f1xx.c</FilePath>
            </File>
          </Files>
        </Group>
        <Group>
          <GroupName>app</GroupName>
          <Files>
            <File>
              <FileName>main.c</FileName>
              <FileType>1</FileType>
              <FilePath>../main.c</FilePath>
            </File>
          </Files>
        </Group>
      </Groups>
    </Target>
    <Target>
      <TargetName>Release</TargetName>
      <ToolsetNumber>0x4</ToolsetNumber>
      <ToolsetName>ARM-ADS</ToolsetName>
      <pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
      <uAC6>1</uAC6>
      <TargetOption>
        <TargetCommonOption>
          <Device>STM32F103CB</Device>
          <Vendor>STMicroelectronics</Vendor>
          <PackID>Keil.STM32F1xx_DFP.2.4.0</PackID>
          <PackURL>http://www.keil.com/pack/</PackURL>
          <Cpu>IRAM(0x20000000,0x00005000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M3") CLOCK(8000000) ELITTLE</Cpu>
          <FlashUtilSpec></FlashUtilSpec>
          <StartupFile></StartupFile>
          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0(195Device:STM32F103CB\STM32F10x_128.FLM))</FlashDriverDll>
          <DeviceId>0</DeviceId>
          <RegisterFile>195Device:STM32F103CB\Include\stm32f10x.h</RegisterFile>
          <MemoryEnv></MemoryEnv>
          <Cmp></Cmp>
          <Asm></Asm>
          <Linker></Linker>
          <OHString></OHString>
          <InfinionOptionDll></InfinionOptionDll>
          <SLE66CMisc></SLE66CMisc>
          <SLE66AMisc></SLE66AMisc>
          <SLE66LinkerMisc></SLE66LinkerMisc>
          <SFDFile>195Device:STM32F103CB\STM32F103xx.svd</SFDFile>
          <bCustSvd>0</bCustSvd>
          <UseEnv>0</UseEnv>
          <BinPath></BinPath>
          <IncludePath></IncludePath>
          <LibPath></LibPath>
          <RegisterFilePath></RegisterFilePath>
          <DBRegisterFilePath></DBRegisterFilePath>
          <TargetStatus>
            <Error>0</Error>
            <ExitCodeStop>0</ExitCodeStop>
            <ButtonStop>0</ButtonStop>
            <NotGenerated>0</NotGenerated>
            <InvalidFlash>1</InvalidFlash>
          </TargetStatus>
          <OutputDirectory>.\OUTPUT\</OutputDirectory>
          <OutputName>project</OutputName>
          <CreateExecutable>1</CreateExecutable>
          <CreateLib>0</CreateLib>
          <CreateHexFile>1</CreateHexFile>
          <DebugInformation>0</DebugInformation>
          <BrowseInformation>0</BrowseInformation>
          <ListingPath></ListingPath>
          <HexFormatSelection>1</HexFormatSelection>
          <Merge32K>0</Merge32K>
          <CreateBatchFile>0</CreateBatchFile>
          <BeforeCompile>
            <RunUserProg1>0</RunUserProg1>
            <RunUserProg2>0</RunUserProg2>
            <UserProg1Name></UserProg1Name>
            <UserProg2Name></UserProg2Name>
            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
            <nStopU1X>0</nStopU1X>
            <nStopU2X>0</nStopU2X>
          </BeforeCompile>
          <BeforeMake>
            <RunUserProg1>0</RunUserProg1>
            <RunUserProg2>0</RunUserProg2>
            <UserProg1Name></UserProg1Name>
            <UserProg2Name></UserProg2Name>
            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
            <nStopB1X>0</nStopB1X>
            <nStopB2X>0</nStopB2X>
          </BeforeMake>
          <AfterMake>
            <RunUserProg1>0</RunUserProg1>
            <RunUserProg2>0</RunUserProg2>
            <UserProg1Name></UserProg1Name>
            <UserProg2Name></UserProg2Name>
            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
            <nStopA1X>0</nStopA1X>
            <nStopA2X>0</nStopA2X>
          </AfterMake>
          <SelectedForBatchBuild>1</SelectedForBatchBuild>
          <SVCSIdString></SVCSIdString>
        </TargetCommonOption>
        <CommonProperty>
          <UseCPPCompiler>0</UseCPPCompiler>
          <RVCTCodeConst>0</RVCTCodeConst>
          <RVCTZI>0</RVCTZI>
          <RVCTOtherData>0</RVCTOtherData>
          <ModuleSelection>0</ModuleSelection>
          <IncludeInBuild>1</IncludeInBuild>
          <AlwaysBuild>0</AlwaysBuild>
          <GenerateAssemblyFile>0</GenerateAssemblyFile>
          <AssembleAssemblyFile>0</AssembleAssemblyFile>
          <PublicsOnly>0</PublicsOnly>
          <StopOnExitCode>3</StopOnExitCode>
          <CustomArgument></CustomArgument>
          <IncludeLibraryModules></IncludeLibraryModules>
          <ComprImg>0</ComprImg>
        </CommonProperty>
        <DllOption>
          <SimDllName>SARMCM3.DLL</SimDllName>
          <SimDllArguments> -REMAP</SimDllArguments>
          <SimDlgDll>DCM.DLL</SimDlgDll>
          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
          <TargetDllName>SARMCM3.DLL</TargetDllName>
          <TargetDllArguments></TargetDllArguments>
          <TargetDlgDll>TCM.DLL</TargetDlgDll>
          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
        </DllOption>
        <DebugOption>
          <OPTHX>
            <HexSelection>1</HexSelection>
            <HexRangeLowAddress>0</HexRangeLowAddress>
            <HexRangeHighAddress>0</HexRangeHighAddress>
            <HexOffset>0</HexOffset>
            <Oh166RecLen>16</Oh166RecLen>
          </OPTHX>
        </DebugOption>
        <Utilities>
          <Flash1>
            <UseTargetDll>1</UseTargetDll>
            <UseExternalTool>0</UseExternalTool>
            <RunIndependent>0</RunIndependent>
            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
            <Capability>1</Capability>
            <DriverSelection>4096</DriverSelection>
          </Flash1>
          <bUseTDR>1</bUseTDR>
          <Flash2>BIN\UL2CM3.DLL</Flash2>
          <Flash3>"" ()</Flash3>
          <Flash4></Flash4>
          <pFcarmOut></pFcarmOut>
          <pFcarmGrp></pFcarmGrp>
          <pFcArmRoot></pFcArmRoot>
          <FcArmLst>0</FcArmLst>
        </Utilities>
        <TargetArmAds>
          <ArmAdsMisc>
            <GenerateListings>0</GenerateListings>
            <asHll>1</asHll>
            <asAsm>1</asAsm>
            <asMacX>1</asMacX>
            <asSyms>1</asSyms>
            <asFals>1</asFals>
            <asDbgD>1</asDbgD>
            <asForm>1</asForm>
            <ldLst>0</ldLst>
            <ldmm>1</ldmm>
            <ldXref>1</ldXref>
            <BigEnd>0</BigEnd>
            <AdsALst>0</AdsALst>
            <AdsACrf>1</AdsACrf>
            <AdsANop>0</AdsANop>
            <AdsANot>0</AdsANot>
            <AdsLLst>0</AdsLLst>
            <AdsLmap>1</AdsLmap>
            <AdsLcgr>1</AdsLcgr>
            <AdsLsym>1</AdsLsym>
            <AdsLszi>1</AdsLszi>
            <AdsLtoi>1</AdsLtoi>
            <AdsLsun>1</AdsLsun>
            <AdsLven>1</AdsLven>
            <AdsLsxf>1</AdsLsxf>
            <RvctClst>0</RvctClst>
            <GenPPlst>0</GenPPlst>
            <AdsCpuType>"Cortex-M3"</AdsCpuType>
            <RvctDeviceName></RvctDeviceName>
            <mOS>0</mOS>
            <uocRom>0</uocRom>
            <uocRam>0</uocRam>
            <hadIROM>1</hadIROM>
            <hadIRAM>1</hadIRAM>
            <hadXRAM>0</hadXRAM>
            <uocXRam>0</uocXRam>
            <RvdsVP>0</RvdsVP>
            <RvdsMve>0</RvdsMve>
            <RvdsCdeCp>0</RvdsCdeCp>
            <hadIRAM2>0</hadIRAM2>
            <hadIROM2>0</hadIROM2>
            <StupSel>8</StupSel>
            <useUlib>1</useUlib>
            <EndSel>0</EndSel>
            <uLtcg>0</uLtcg>
            <nSecure>0</nSecure>
            <RoSelD>3</RoSelD>
            <RwSelD>3</RwSelD>
            <CodeSel>0</CodeSel>
            <OptFeed>0</OptFeed>
            <NoZi1>0</NoZi1>
            <NoZi2>0</NoZi2>
            <NoZi3>0</NoZi3>
            <NoZi4>0</NoZi4>
            <NoZi5>0</NoZi5>
            <Ro1Chk>0</Ro1Chk>
            <Ro2Chk>0</Ro2Chk>
            <Ro3Chk>0</Ro3Chk>
            <Ir1Chk>1</Ir1Chk>
            <Ir2Chk>0</Ir2Chk>
            <Ra1Chk>0</Ra1Chk>
            <Ra2Chk>0</Ra2Chk>
            <Ra3Chk>0</Ra3Chk>
            <Im1Chk>1</Im1Chk>
            <Im2Chk>0</Im2Chk>
            <OnChipMemories>
              <Ocm1>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </Ocm1>
              <Ocm2>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </Ocm2>
              <Ocm3>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </Ocm3>
              <Ocm4>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </Ocm4>
              <Ocm5>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </Ocm5>
              <Ocm6>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </Ocm6>
              <IRAM>
                <Type>0</Type>
                <StartAddress>0x20000000</StartAddress>
                <Size>0x5000</Size>
              </IRAM>
              <IROM>
                <Type>1</Type>
                <StartAddress>0x8000000</StartAddress>
                <Size>0x20000</Size>
              </IROM>
              <XRAM>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </XRAM>
              <OCR_RVCT1>
                <Type>1</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </OCR_RVCT1>
              <OCR_RVCT2>
                <Type>1</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </OCR_RVCT2>
              <OCR_RVCT3>
                <Type>1</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </OCR_RVCT3>
              <OCR_RVCT4>
                <Type>1</Type>
                <StartAddress>0x8000000</StartAddress>
                <Size>0x20000</Size>
              </OCR_RVCT4>
              <OCR_RVCT5>
                <Type>1</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </OCR_RVCT5>
              <OCR_RVCT6>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </OCR_RVCT6>
              <OCR_RVCT7>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </OCR_RVCT7>
              <OCR_RVCT8>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </OCR_RVCT8>
              <OCR_RVCT9>
                <Type>0</Type>
                <StartAddress>0x20000000</StartAddress>
                <Size>0x5000</Size>
              </OCR_RVCT9>
              <OCR_RVCT10>
                <Type>0</Type>
                <StartAddress>0x0</StartAddress>
                <Size>0x0</Size>
              </OCR_RVCT10>
            </OnChipMemories>
            <RvctStartVector></RvctStartVector>
          </ArmAdsMisc>
          <Cads>
            <interw>1</interw>
            <Optim>6</Optim>
            <oTime>0</oTime>
            <SplitLS>0</SplitLS>
            <OneElfS>1</OneElfS>
            <Strict>0</Strict>
            <EnumInt>0</EnumInt>
            <PlainCh>0</PlainCh>
            <Ropi>0</Ropi>
            <Rwpi>0</Rwpi>
            <wLevel>2</wLevel>
            <uThumb>0</uThumb>
            <uSurpInc>0</uSurpInc>
            <uC99>1</uC99>
            <uGnu>0</uGnu>
            <useXO>0</useXO>
            <v6Lang>6</v6Lang>
            <v6LangP>9</v6LangP>
            <vShortEn>1</vShortEn>
            <vShortWch>1</vShortWch>
            <v6Lto>1</v6Lto>
            <v6WtE>1</v6WtE>
            <v6Rtti>0</v6Rtti>
            <VariousControls>
              <MiscControls>-Wno-missing-prototypes -Wno-unreachable-code-return</MiscControls>
              $def_set1 NDEBUG, USE_SWD=0, $def_set2
              <Undefine></Undefine>
              <IncludePath>..</IncludePath>
            </VariousControls>
          </Cads>
          <Aads>
            <interw>1</interw>
            <Ropi>0</Ropi>
            <Rwpi>0</Rwpi>
            <thumb>0</thumb>
            <SplitLS>0</SplitLS>
            <SwStkChk>0</SwStkChk>
            <NoWarn>0</NoWarn>
            <uSurpInc>0</uSurpInc>
            <useXO>0</useXO>
            <ClangAsOpt>4</ClangAsOpt>
            <VariousControls>
              <MiscControls></MiscControls>
              <Define></Define>
              <Undefine></Undefine>
              <IncludePath></IncludePath>
            </VariousControls>
          </Aads>
          <LDads>
            <umfTarg>1</umfTarg>
            <Ropi>0</Ropi>
            <Rwpi>0</Rwpi>
            <noStLib>0</noStLib>
            <RepFail>1</RepFail>
            <useFile>0</useFile>
            <TextAddressRange></TextAddressRange>
            <DataAddressRange></DataAddressRange>
            <pXoBase></pXoBase>
            <ScatterFile></ScatterFile>
            <IncludeLibs></IncludeLibs>
            <IncludeLibsPath></IncludeLibsPath>
            <Misc></Misc>
            <LinkerInputFile></LinkerInputFile>
            <DisabledWarnings></DisabledWarnings>
          </LDads>
        </TargetArmAds>
      </TargetOption>
      <Groups>
        <Group>
          <GroupName>startup</GroupName>
          <Files>
            <File>
              <FileName>startup_stm32f103xb.s</FileName>
              <FileType>2</FileType>
              <FilePath>startup_stm32f103xb.s</FilePath>
            </File>
            <File>
              <FileName>system_stm32f1xx.c</FileName>
              <FileType>1</FileType>
              <FilePath>../system_stm32f1xx.c</FilePath>
            </File>
          </Files>
        </Group>
        <Group>
          <GroupName>app</GroupName>
          <Files>
            <File>
              <FileName>main.c</FileName>
              <FileType>1</FileType>
              <FilePath>../main.c</FilePath>
            </File>
          </Files>
        </Group>
      </Groups>
    </Target>
  </Targets>
  <RTE>
    <apis/>
    <components/>
    <files/>
  </RTE>
</Project>
MDK_CONFIG
  cd ..
  break
fi
done

for arg in "$@"; do
    if [ "$arg" = "ses" ]; then
        cat << SES_CONFIG > project.emProject
<!DOCTYPE CrossStudio_Project_File>
<solution Name="project" target="8" version="2">
  <configuration Name="Debug" inherited_configurations="Internal;Debug" />
  <configuration Name="Internal" Platform="ARM" hidden="Yes" />
  <configuration Name="Release" inherited_configurations="Internal;Release" />
  <project Name="BluePill">
    <configuration
      Name="Common"
      WARNING_LEVEL="4 (All)"
      arm_assembler_variant="SEGGER"
      arm_compiler_variant="SEGGER"
      arm_core_type="Cortex-M3"
      arm_endian="Little"
      arm_linker_treat_warnings_as_errors="Yes"
      arm_linker_variant="SEGGER"
      arm_target_device_name="STM32F103CB"
      arm_target_interface_type="SWD"
      c_preprocessor_definitions="STM32F103xB;USE_ALL"
      debug_start_from_entry_point_symbol="No"
      debug_target_connection="J-Link"
      gcc_c_language_standard="gnu17"
      gcc_cplusplus_language_standard="gnu++20"
      gcc_enable_all_warnings="Yes"
      gcc_strict_prototypes_warning="Yes"
      gcc_uninitialized_variables_warning="Yes"
      gcc_unused_variable_warning="Yes"
      link_linker_script_file="\$(StudioDir)/samples/SEGGER_Flash.icf"
      link_map_file="Detailed"
      linker_log_file="Yes"
      linker_output_format="bin"
      linker_section_placements_segments="FLASH1 RX 0x08000000 0x00020000;RAM1 RWX 0x20000000 0x00005000;"
      project_type="Executable" />
    <configuration
      Name="Debug"
      gcc_debugging_level="Level 3"
      gcc_dwarf_version="dwarf-5" />
    <configuration
      LIBRARY_IO_TYPE="SEMIHOST (host-formatted)"
      Name="Internal" />
    <configuration
      Name="Release"
      gcc_debugging_level="None"
      gcc_dwarf_version="None"
      gcc_optimization_level="Level 2 for size"
      gcc_strip_symbols="Yes"
      link_dedupe_code="Yes"
      link_dedupe_data="Yes"
      link_inline="Yes"
      linker_strip_debug_information="Yes" />
    <folder Name="Internal Files">
      <file file_name="\$(StudioDir)/samples/Cortex_M_Startup.s" />
      <file file_name="\$(StudioDir)/samples/SEGGER_THUMB_Startup.s" />
    </folder>
    <folder Name="app">
      <file file_name="./main.c" />
    </folder>
    <folder Name="startup">
      <file file_name="./system_stm32f1xx.c" />
    </folder>
  </project>
</solution>
SES_CONFIG
        break
    fi
done

#
# generate main.h
#

cat <<MAIN_H >main.h
#ifndef __MAIN_H
#define __MAIN_H

#include "stm32f1xx.h"

#ifdef __cplusplus
 extern C {
#endif

#define NO  0
#define YES (!NO)

/* *********************************************************************************** */
/* ******** Uncomment lines below if these features are required ********************* */
/* *********************************************************************************** */
#if defined(USE_ALL)                       /*                                          */

  #ifndef USE_HSE
    #define USE_HSE                     1  /* Use crystal oscillator as clock source   */
  #endif

  #ifndef USE_PLL
    #define USE_PLL                     1  /* Use PLL as system clock source           */
  #endif

  #ifndef USE_LSE
    #define USE_LSE                     1  /* Use LSE as RTC clock source              */
  #endif

  #ifndef USE_ADC
    #define USE_ADC                     1  /* Configure ADC1 peripheral                */
  #endif

  #ifndef USE_USART
    #define USE_USART                   1  /* Configure USART1 for transmit/receive    */
  #endif

  #ifndef USE_I2C
    #define USE_I2C                     1  /* Configure I2C1 with 100 kHz clock speed  */
  #endif                                                                    

  #ifndef USE_SPI
    #define USE_SPI                     1  /* Configure SPI1                           */
  #endif

  #ifndef USE_BTN
    #define USE_BTN                     1  /* Handle buttons connected to PB1 and PB2  */
  #endif

  #ifndef USE_RTC
    #define USE_RTC                     1  /* Configure and run RTC                    */
  #endif

  #ifndef USE_TIM2
    #define USE_TIM2                    1  /* Configure and run TIM2                   */
  #endif

  #ifndef USE_DMA
    #define USE_DMA                     1  /* Use DMA where it is possible             */
  #endif

  #ifndef USE_CRC
    #define USE_CRC                     1  /* Enable CRC computation                   */
  #endif

  #ifndef USE_RNG
    #define USE_RNG                     1  /* Enable random number generation          */
  #endif

  #ifndef USE_IWDG
    #define USE_IWDG                    1  /* Enable independent hardware watchdog     */
  #endif

  #ifndef USE_WWDG
    #define USE_WWDG                    0  /* Enable window hardware watchdog          */
  #endif

  #ifndef USE_EXTI
    #define USE_EXTI                    1  /* Use external interrupt                   */
  #endif

  #ifndef USE_FLASH
    #define USE_FLASH                   1  /* Add feature to write data to flash       */
  #endif

  #ifndef USE_SWD
    #define USE_SWD                     1  /* Use SWD pins for debugging               */
  #endif

  #ifndef OVRCLK
    #define OVRCLK                      1  /* Overclock microcontroller (112 MHz)      */
  #endif
#endif                                     /*                                          */
/* *********************************************************************************** */
/* ********  Alternatively, define them as command-line parameters in Makefile  ****** */
/* *********************************************************************************** */

#define D11 (*DMA1_Channel1) /* 0x40020008 */
#define D12 (*DMA1_Channel2) /* 0x4002001C */
#define D13 (*DMA1_Channel3) /* 0x40020030 */
#define D14 (*DMA1_Channel4) /* 0x40020044 */
#define D15 (*DMA1_Channel5) /* 0x40020058 */
#define D16 (*DMA1_Channel6) /* 0x4002006C */
#define D17 (*DMA1_Channel7) /* 0x40020080 */

#define A1  (*ADC1)   /* 0x40012400 */
#define A2  (*ADC2)   /* 0x40012800 */
#define A   (*AFIO)   /* 0x40010000 */

#define B   (*BKP)    /* 0x40006C00 */
#define C   (*CRC)    /* 0x40023000 */
#define C1  (*CAN1)   /* 0x40006400 */
#define D   (*DBGMCU) /* 0xE0042000 */
#define E   (*EXTI)   /* 0x40010400 */
#define F   (*FLASH)  /* 0x40022000 */

#define PA  (*GPIOA)  /* 0x40010800 */
#define PB  (*GPIOB)  /* 0x40010C00 */
#define PC  (*GPIOC)  /* 0x40011000 */
#define PD  (*GPIOD)  /* 0x40011400 */

#define I1  (*I2C1)   /* 0x40005400 */
#define I2  (*I2C2)   /* 0x40005800 */
#define I   (*IWDG)   /* 0x40003000 */

#define O   (*OB)     /* 0x1FFFF800 */

#define P   (*PWR)    /* 0x40007000 */
#define R   (*RCC)    /* 0x40021000 */
#define RT  (*RTC)    /* 0x40002800 */

#define S1  (*SPI1)   /* 0x40013000 */
#define S2  (*SPI2)   /* 0x40003800 */

#define T1  (*TIM1)   /* 0x40012C00 */
#define T2  (*TIM2)   /* 0x40000000 */
#define T3  (*TIM3)   /* 0x40000400 */
#define T4  (*TIM4)   /* 0x40000800 */

#define U   (*USB)    /* 0x40005C00 */

#define U1  (*USART1) /* 0x40013800 */
#define U2  (*USART2) /* 0x40004400 */
#define U3  (*USART3) /* 0x40004800 */

#define W   (*WWDG)   /* 0x40002C00 */


#define PORT_CFG(PORT, CFG)             *(__IO uint64_t*) GPIO##PORT##_BASE = (CFG)

#define PORT_CONFIG(PORT, CFG, STATE)   if (YES) {                                      \\
                                          if (CFG) { PORT_CFG(PORT, CFG); }             \\
                                          if (STATE) { GPIO##PORT->BSRR = (STATE); }    \\
                                        } else (void) NO

#define PIN_CFG(PIN, MODE)              ((MODE) << ((PIN) * 4))
                                                                                       /*
    In input mode (MODE[1:0] = 00):

  00: Analog mode
  01: Floating input (reset state)
  10: Input with pull-up / pull-down
  11: Reserved
                                                                                       */
#define I_ANALOG                        (0ULL << 2)
#define I_FLOAT                         (1ULL << 2)
#define I_PULL                          (2ULL << 2)
                                                                                       /*
    In output mode (MODE[1:0] > 00):

  00: General purpose output push-pull
  01: General purpose output Open-drain
  10: Alternate function output Push-pull
  11: Alternate function output Open-drain
                                                                                       */
#define O_PP                            (0ULL << 2)
#define O_OD                            (1ULL << 2)
#define O_AF                            (2ULL << 2)
                                                                                       /*
  MODEy[1:0]: Port x mode bits (y = 0 .. 7)
  These bits are written by software to configure the corresponding I/O port.
  Refer to Table 20: Port bit configuration table.

  00: Input mode (reset state)
  01: Output mode, max speed 10 MHz.
  10: Output mode, max speed 2 MHz.
  11: Output mode, max speed 50 MHz.
                                                                                       */
#define O_10MHZ                         1ULL
#define O_2MHZ                          2ULL
#define O_50MHZ                         3ULL

#define DOWN                            GPIO_BSRR_BR
#define UP                              GPIO_BSRR_BS

#define CAT(A, B)                       A ## B
#define SW_PIN(PORT, PIN, STATE)        GPIO ## PORT->BSRR = CAT(STATE, PIN)
#define PULL(PIN, STATE)                CAT(STATE, PIN)
#define HIGH(PIN)                       GPIO_BSRR_BS ## PIN
#define LOW(PIN)                        GPIO_BSRR_BR ## PIN

#define PIN_HIGH(PIN)                   GPIO_BSRR_BS ## PIN
#define PIN_LOW(PIN)                    GPIO_BSRR_BR ## PIN
#define PULL_UP(PIN)                    GPIO_BSRR_BS ## PIN
#define PULL_DOWN(PIN)                  GPIO_BSRR_BR ## PIN

#define _BR(PIN)                        GPIO_BSRR_BR ## PIN
#define BR(PIN)                         _BR(PIN)
#define _BS(PIN)                        GPIO_BSRR_BS ## PIN
#define BS(PIN)                         _BS(PIN)
#define _ODR(PIN)                       GPIO_ODR_ODR ## PIN
#define ODR(PIN)                        _ODR(PIN)

#define ATOMIC_OUT(PORT, DATA)          PORT->BSRR = 0x00FF0000 | (DATA)
#define READ_PIN(PORT, PIN)             (GPIO ## PORT->IDR & GPIO_IDR_IDR ## PIN)

/**
 * @brief Compile-time validation helper for bit-banding macros
 * 
 * @details Validates that BIT parameter contains exactly ONE bit set.
 *          Uses __builtin_popcount() to count the number of '1' bits.
 * 
 * Validation logic:
 *   - __builtin_popcount(BIT) == 1  -> true  -> !!(true)  = 1 -> 1/1 = 1 (OK)
 *   - __builtin_popcount(BIT) != 1  -> false -> !!(false) = 0 -> 1/0 (ERROR)
 * 
 * @note Actual compile errors when invalid BIT value is used:
 *       - GCC/ARM GCC:  "error: division by zero [-Werror=div-by-zero]"
 *       - MDK-ARM/Clang: "error: division by zero is undefined [-Werror,-Wdivision-by-zero]"
 * 
 *       This means: BIT parameter has ZERO bits or MULTIPLE bits set
 * 
 * @par Valid examples:
 *      0x01, 0x08, 0x100, (1U << 5)  - exactly one bit
 * 
 * @par Invalid examples:
 *      0x00 (no bits), 0x03 (two bits), 0xFF (eight bits)
 */
#define VALIDATE_SINGLE_BIT(BIT) \
    (1 / (!!(__builtin_popcount(BIT) == 1)))

/**
 * @brief Core bit-banding address calculation macro
 * 
 * @details Calculates bit-band alias address for atomic bit access.
 *          Includes compile-time validation that BIT has exactly one bit set.
 *          Validation result is multiplied by 0U to not affect address calculation,
 *          but forces compile-time evaluation of VALIDATE_SINGLE_BIT.
 * 
 * @param AREA Memory area prefix (SRAM or PERIPH)
 * @param ADDR Address of the register or variable
 * @param BIT  Bit mask with exactly ONE bit set (e.g., (1U << 5))
 * 
 * @return Pointer to bit-band alias address
 */
#define GET_BIT(AREA, ADDR, BIT)                                        \\
    (*(__IO uint32_t *)(                                                \\
        (AREA##_BB_BASE +                                               \\
        32U * ((uint32_t)&(ADDR) - AREA##_BASE) +                       \\
        4U * __builtin_ctz(BIT) +                                       \\
        0U * VALIDATE_SINGLE_BIT(BIT))                                  \\
     ))

/* SRAM bit access macros                                               */

/** @brief Read single bit from SRAM variable via bit-banding           */
#define READ_MEM_BIT(VAR, BIT)          GET_BIT(SRAM, VAR, BIT)

/** @brief Write single bit to SRAM variable via bit-banding            */
#define WRITE_MEM_BIT(VAR, BIT, VAL)    READ_MEM_BIT(VAR, BIT) = (VAL)

/** @brief Set single bit in SRAM variable to 1 via bit-banding         */
#define SET_MEM_BIT(VAR, BIT)           WRITE_MEM_BIT(VAR, BIT, 1)

/** @brief Clear single bit in SRAM variable to 0 via bit-banding       */
#define CLEAR_MEM_BIT(VAR, BIT)         WRITE_MEM_BIT(VAR, BIT, 0)

/* Peripheral bit access macros                                         */

/** @brief Read single bit from peripheral register via bit-banding     */
#define READ_REG_BIT(REG, BIT)          GET_BIT(PERIPH, REG, BIT)

/** @brief Write single bit to peripheral register via bit-banding      */
#define WRITE_REG_BIT(REG, BIT, VAL)    READ_REG_BIT(REG, BIT) = (VAL)

/** @brief Set single bit in peripheral register to 1 via bit-banding   */
#define SET_REG_BIT(REG, BIT)           WRITE_REG_BIT(REG, BIT, 1)

/** @brief Clear single bit in peripheral register to 0 via bit-banding */
#define CLEAR_REG_BIT(REG, BIT)         WRITE_REG_BIT(REG, BIT, 0)

#define GET_TICK()                      (SysTick->CTRL >> SysTick_CTRL_COUNTFLAG_Pos)
#define DELAY_MS(MS)                    for (unsigned _ = (SysTick->CTRL, (MS)); _; _ -= GET_TICK()) (void)0

#define STOPWATCH_INIT()                do {                                              \\
                                          CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; \\
                                          DWT->CYCCNT = 0;                                \\
                                          DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;            \\
                                        } while (0)

#define STOPWATCH_START(VAR)            do { (VAR) = DWT->CYCCNT; } while(0)
#define STOPWATCH_STOP(VAR)             do { (VAR) = DWT->CYCCNT - (VAR); } while(0)

__STATIC_INLINE void stopwatch_reset(void) {
  CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; /* Enable Data Watchpoint and Trace */
  DWT->CYCCNT = 0;                                /* Reset CPU cycle counter          */
  DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;            /* Enable CPU cycle counter         */
}

// Delay for a specific number of CPU cycles (minimum ~5 cycles overhead)
#define DELAY_CYCLES(N)                 for(unsigned _ = DWT->CYCCNT; (DWT->CYCCNT - _) < (N);) (void)0

// Nanoseconds delay (minimum ~100ns due to overhead)
#define DELAY_NS(NS)                    DELAY_CYCLES((uint32_t)(((uint64_t)(NS) * HCLK) / 1000000000UL))

// Microseconds delay (minimum ~1Р’Вµs recommended)
#define DELAY_US(US)                    DELAY_CYCLES((uint32_t)(((uint64_t)(US) * HCLK) / 1000000UL))

#if 0
// Milliseconds delay
#define DELAY_MS(MS)                    DELAY_CYCLES((uint32_t)((MS) * (HCLK / 1000UL)))
#endif

__STATIC_FORCEINLINE void delay_ms(unsigned ms) {(void)SysTick->CTRL; while(ms -= GET_TICK());}


#define WAIT_FOR_FLAG(REG, FLAG, TIMEOUT) do {                                  \\
          unsigned timeout = SysTick->CTRL >> (SysTick_CTRL_COUNTFLAG_Pos + 1); \\
          while(((REG) & (FLAG)) != (FLAG)) {                                   \\
            timeout += GET_TICK();                                              \\
            if (timeout > (TIMEOUT)) {                                          \\
              return ERROR;                                                     \\
            }                                                                   \\
          }                                                                     \\
        } while(NO)


// --- Universal BITS Macro ---
// Helper macro: paste together PREFIX_, REG, and BF to form a bitfield macro name
#define _BITS_ONE(PREFIX_, REG, BF) PREFIX_##REG##_##BF

// Recursive macros to combine 1В–16 bitfields using the '|' operator
#define _BITS_1(PREFIX_, REG, BF) _BITS_ONE(PREFIX_, REG, BF)
#define _BITS_2(PREFIX_, REG, BF, ...) _BITS_ONE(PREFIX_, REG, BF) | _BITS_1(PREFIX_, REG, __VA_ARGS__)
#define _BITS_3(PREFIX_, REG, BF, ...) _BITS_ONE(PREFIX_, REG, BF) | _BITS_2(PREFIX_, REG, __VA_ARGS__)
#define _BITS_4(PREFIX_, REG, BF, ...) _BITS_ONE(PREFIX_, REG, BF) | _BITS_3(PREFIX_, REG, __VA_ARGS__)
#define _BITS_5(PREFIX_, REG, BF, ...) _BITS_ONE(PREFIX_, REG, BF) | _BITS_4(PREFIX_, REG, __VA_ARGS__)
#define _BITS_6(PREFIX_, REG, BF, ...) _BITS_ONE(PREFIX_, REG, BF) | _BITS_5(PREFIX_, REG, __VA_ARGS__)
#define _BITS_7(PREFIX_, REG, BF, ...) _BITS_ONE(PREFIX_, REG, BF) | _BITS_6(PREFIX_, REG, __VA_ARGS__)
#define _BITS_8(PREFIX_, REG, BF, ...) _BITS_ONE(PREFIX_, REG, BF) | _BITS_7(PREFIX_, REG, __VA_ARGS__)
#define _BITS_9(PREFIX_, REG, BF, ...) _BITS_ONE(PREFIX_, REG, BF) | _BITS_8(PREFIX_, REG, __VA_ARGS__)
#define _BITS_10(PREFIX_, REG, BF, ...) _BITS_ONE(PREFIX_, REG, BF) | _BITS_9(PREFIX_, REG, __VA_ARGS__)
#define _BITS_11(PREFIX_, REG, BF, ...) _BITS_ONE(PREFIX_, REG, BF) | _BITS_10(PREFIX_, REG, __VA_ARGS__)
#define _BITS_12(PREFIX_, REG, BF, ...) _BITS_ONE(PREFIX_, REG, BF) | _BITS_11(PREFIX_, REG, __VA_ARGS__)
#define _BITS_13(PREFIX_, REG, BF, ...) _BITS_ONE(PREFIX_, REG, BF) | _BITS_12(PREFIX_, REG, __VA_ARGS__)
#define _BITS_14(PREFIX_, REG, BF, ...) _BITS_ONE(PREFIX_, REG, BF) | _BITS_13(PREFIX_, REG, __VA_ARGS__)
#define _BITS_15(PREFIX_, REG, BF, ...) _BITS_ONE(PREFIX_, REG, BF) | _BITS_14(PREFIX_, REG, __VA_ARGS__)
#define _BITS_16(PREFIX_, REG, BF, ...) _BITS_ONE(PREFIX_, REG, BF) | _BITS_15(PREFIX_, REG, __VA_ARGS__)

// Macro to count the number of variadic arguments (up to 16)
#define _BITS_NARG(...) _BITS_NARG_(__VA_ARGS__,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1)
#define _BITS_NARG_(_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,_11,_12,_13,_14,_15,_16,N,...) N

// Macro dispatcher: chooses the correct _BITS_n macro based on argument count
#define _BITS_CHOOSER2(count) _BITS_##count
#define _BITS_CHOOSER1(count) _BITS_CHOOSER2(count)
#define _BITS_CHOOSER(count)  _BITS_CHOOSER1(count)

// Main macro: expands to a mask of all requested bitfields for a given peripheral register
#define BITS(PREFIX_, REG, ...)     (_BITS_CHOOSER(_BITS_NARG(__VA_ARGS__))(PREFIX_, REG, __VA_ARGS__))

// --- Peripheral Type Wrappers ---
// These wrappers make it easy to use the BITS macro for each peripheral type.
// Example: RCC_BITS(APB2ENR, IOPAEN, AFIOEN) expands to (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN)

#define RCC_BITS(reg, ...)      BITS(RCC_, reg, __VA_ARGS__)    // For RCC registers
#define GPIO_BITS(reg, ...)     BITS(GPIO_, reg, __VA_ARGS__)   // For GPIO registers
#define AFIO_BITS(reg, ...)     BITS(AFIO_, reg, __VA_ARGS__)   // For AFIO registers
#define TIM_BITS(reg, ...)      BITS(TIM_, reg, __VA_ARGS__)    // For TIM registers
#define USART_BITS(reg, ...)    BITS(USART_, reg, __VA_ARGS__)  // For USART registers
#define UART_BITS(reg, ...)     BITS(UART_, reg, __VA_ARGS__)   // For UART registers
#define SPI_BITS(reg, ...)      BITS(SPI_, reg, __VA_ARGS__)    // For SPI registers
#define I2C_BITS(reg, ...)      BITS(I2C_, reg, __VA_ARGS__)    // For I2C registers
#define CAN_BITS(reg, ...)      BITS(CAN_, reg, __VA_ARGS__)    // For CAN registers
#define ADC_BITS(reg, ...)      BITS(ADC_, reg, __VA_ARGS__)    // For ADC registers
#define DAC_BITS(reg, ...)      BITS(DAC_, reg, __VA_ARGS__)    // For DAC registers
#define CRC_BITS(reg, ...)      BITS(CRC_, reg, __VA_ARGS__)    // For CRC registers
#define USB_BITS(reg, ...)      BITS(USB_, reg, __VA_ARGS__)    // For USB registers
#define BKP_BITS(reg, ...)      BITS(BKP_, reg, __VA_ARGS__)    // For BKP registers
#define PWR_BITS(reg, ...)      BITS(PWR_, reg, __VA_ARGS__)    // For PWR registers
#define FLASH_BITS(reg, ...)    BITS(FLASH_, reg, __VA_ARGS__)  // For FLASH registers
#define DBGMCU_BITS(reg, ...)   BITS(DBGMCU_, reg, __VA_ARGS__) // For DBGMCU registers
#define WWDG_BITS(reg, ...)     BITS(WWDG_, reg, __VA_ARGS__)   // For WWDG registers
#define IWDG_BITS(reg, ...)     BITS(IWDG_, reg, __VA_ARGS__)   // For IWDG registers
#define RTC_BITS(reg, ...)      BITS(RTC_, reg, __VA_ARGS__)    // For RTC registers
#define EXTI_BITS(reg, ...)     BITS(EXTI_, reg, __VA_ARGS__)   // For EXTI registers
#define DMA_BITS(reg, ...)      BITS(DMA_, reg, __VA_ARGS__)    // For DMA registers

// === Register Shortcuts ===
// The following are convenient macros for common registers,
// reducing the need to repeat BITS(...) explicitly.
// Grouped per peripheral type for organization.

// --- RCC ---
#define RCC_CR(...)           BITS(RCC_, CR, __VA_ARGS__)
#define RCC_CFGR(...)         BITS(RCC_, CFGR, __VA_ARGS__)
#define RCC_CIR(...)          BITS(RCC_, CIR, __VA_ARGS__)
#define RCC_APB2RSTR(...)     BITS(RCC_, APB2RSTR, __VA_ARGS__)
#define RCC_APB1RSTR(...)     BITS(RCC_, APB1RSTR, __VA_ARGS__)
#define RCC_AHBENR(...)       BITS(RCC_, AHBENR, __VA_ARGS__)
#define RCC_APB2ENR(...)      BITS(RCC_, APB2ENR, __VA_ARGS__)
#define RCC_APB1ENR(...)      BITS(RCC_, APB1ENR, __VA_ARGS__)
#define RCC_BDCR(...)         BITS(RCC_, BDCR, __VA_ARGS__)
#define RCC_CSR(...)          BITS(RCC_, CSR, __VA_ARGS__)

// --- GPIO ---
#define GPIO_CRL(...)         BITS(GPIO_, CRL, __VA_ARGS__)
#define GPIO_CRH(...)         BITS(GPIO_, CRH, __VA_ARGS__)
#define GPIO_IDR(...)         BITS(GPIO_, IDR, __VA_ARGS__)
#define GPIO_ODR(...)         BITS(GPIO_, ODR, __VA_ARGS__)
#define GPIO_BSRR(...)        BITS(GPIO_, BSRR, __VA_ARGS__)
#define GPIO_BRR(...)         BITS(GPIO_, BRR, __VA_ARGS__)
#define GPIO_LCKR(...)        BITS(GPIO_, LCKR, __VA_ARGS__)

// --- AFIO ---
#define AFIO_EVCR(...)        BITS(AFIO_, EVCR, __VA_ARGS__)
#define AFIO_MAPR(...)        BITS(AFIO_, MAPR, __VA_ARGS__)
#define AFIO_EXTICR1(...)     BITS(AFIO_, EXTICR1, __VA_ARGS__)
#define AFIO_EXTICR2(...)     BITS(AFIO_, EXTICR2, __VA_ARGS__)
#define AFIO_EXTICR3(...)     BITS(AFIO_, EXTICR3, __VA_ARGS__)
#define AFIO_EXTICR4(...)     BITS(AFIO_, EXTICR4, __VA_ARGS__)
#define AFIO_MAPR2(...)       BITS(AFIO_, MAPR2, __VA_ARGS__)

// --- TIM (general purpose and advanced) ---
#define TIM_CR1(...)          BITS(TIM_, CR1, __VA_ARGS__)
#define TIM_CR2(...)          BITS(TIM_, CR2, __VA_ARGS__)
#define TIM_SMCR(...)         BITS(TIM_, SMCR, __VA_ARGS__)
#define TIM_DIER(...)         BITS(TIM_, DIER, __VA_ARGS__)
#define TIM_BDTR(...)         BITS(TIM_, BDTR, __VA_ARGS__)
#define TIM_SR(...)           BITS(TIM_, SR, __VA_ARGS__)
#define TIM_EGR(...)          BITS(TIM_, EGR, __VA_ARGS__)
#define TIM_CCMR1(...)        BITS(TIM_, CCMR1, __VA_ARGS__)
#define TIM_CCMR2(...)        BITS(TIM_, CCMR2, __VA_ARGS__)
#define TIM_CCER(...)         BITS(TIM_, CCER, __VA_ARGS__)
#define TIM_CNT(...)          BITS(TIM_, CNT, __VA_ARGS__)
#define TIM_PSC(...)          BITS(TIM_, PSC, __VA_ARGS__)
#define TIM_ARR(...)          BITS(TIM_, ARR, __VA_ARGS__)
#define TIM_CCR1(...)         BITS(TIM_, CCR1, __VA_ARGS__)
#define TIM_CCR2(...)         BITS(TIM_, CCR2, __VA_ARGS__)
#define TIM_CCR3(...)         BITS(TIM_, CCR3, __VA_ARGS__)
#define TIM_CCR4(...)         BITS(TIM_, CCR4, __VA_ARGS__)
#define TIM_DCR(...)          BITS(TIM_, DCR, __VA_ARGS__)
#define TIM_DMAR(...)         BITS(TIM_, DMAR, __VA_ARGS__)

// --- USART ---
#define USART_SR(...)         BITS(USART_, SR, __VA_ARGS__)
#define USART_DR(...)         BITS(USART_, DR, __VA_ARGS__)
#define USART_BRR(...)        BITS(USART_, BRR, __VA_ARGS__)
#define USART_CR1(...)        BITS(USART_, CR1, __VA_ARGS__)
#define USART_CR2(...)        BITS(USART_, CR2, __VA_ARGS__)
#define USART_CR3(...)        BITS(USART_, CR3, __VA_ARGS__)
#define USART_GTPR(...)       BITS(USART_, GTPR, __VA_ARGS__)

// --- SPI ---
#define SPI_CR1(...)          BITS(SPI_, CR1, __VA_ARGS__)
#define SPI_CR2(...)          BITS(SPI_, CR2, __VA_ARGS__)
#define SPI_SR(...)           BITS(SPI_, SR, __VA_ARGS__)
#define SPI_DR(...)           BITS(SPI_, DR, __VA_ARGS__)
#define SPI_CRCPR(...)        BITS(SPI_, CRCPR, __VA_ARGS__)
#define SPI_RXCRCR(...)       BITS(SPI_, RXCRCR, __VA_ARGS__)
#define SPI_TXCRCR(...)       BITS(SPI_, TXCRCR, __VA_ARGS__)
#define SPI_I2SCFGR(...)      BITS(SPI_, I2SCFGR, __VA_ARGS__)
#define SPI_I2SPR(...)        BITS(SPI_, I2SPR, __VA_ARGS__)

// --- I2C ---
#define I2C_CR1(...)          BITS(I2C_, CR1, __VA_ARGS__)
#define I2C_CR2(...)          BITS(I2C_, CR2, __VA_ARGS__)
#define I2C_OAR1(...)         BITS(I2C_, OAR1, __VA_ARGS__)
#define I2C_OAR2(...)         BITS(I2C_, OAR2, __VA_ARGS__)
#define I2C_DR(...)           BITS(I2C_, DR, __VA_ARGS__)
#define I2C_SR1(...)          BITS(I2C_, SR1, __VA_ARGS__)
#define I2C_SR2(...)          BITS(I2C_, SR2, __VA_ARGS__)
#define I2C_CCR(...)          BITS(I2C_, CCR, __VA_ARGS__)
#define I2C_TRISE(...)        BITS(I2C_, TRISE, __VA_ARGS__)

// --- ADC ---
#define ADC_SR(...)           BITS(ADC_, SR, __VA_ARGS__)
#define ADC_CR1(...)          BITS(ADC_, CR1, __VA_ARGS__)
#define ADC_CR2(...)          BITS(ADC_, CR2, __VA_ARGS__)
#define ADC_SMPR1(...)        BITS(ADC_, SMPR1, __VA_ARGS__)
#define ADC_SMPR2(...)        BITS(ADC_, SMPR2, __VA_ARGS__)
#define ADC_JOFR1(...)        BITS(ADC_, JOFR1, __VA_ARGS__)
#define ADC_JOFR2(...)        BITS(ADC_, JOFR2, __VA_ARGS__)
#define ADC_JOFR3(...)        BITS(ADC_, JOFR3, __VA_ARGS__)
#define ADC_JOFR4(...)        BITS(ADC_, JOFR4, __VA_ARGS__)
#define ADC_HTR(...)          BITS(ADC_, HTR, __VA_ARGS__)
#define ADC_LTR(...)          BITS(ADC_, LTR, __VA_ARGS__)
#define ADC_SQR1(...)         BITS(ADC_, SQR1, __VA_ARGS__)
#define ADC_SQR2(...)         BITS(ADC_, SQR2, __VA_ARGS__)
#define ADC_SQR3(...)         BITS(ADC_, SQR3, __VA_ARGS__)
#define ADC_JSQR(...)         BITS(ADC_, JSQR, __VA_ARGS__)
#define ADC_JDR1(...)         BITS(ADC_, JDR1, __VA_ARGS__)
#define ADC_JDR2(...)         BITS(ADC_, JDR2, __VA_ARGS__)
#define ADC_JDR3(...)         BITS(ADC_, JDR3, __VA_ARGS__)
#define ADC_JDR4(...)         BITS(ADC_, JDR4, __VA_ARGS__)
#define ADC_DR(...)           BITS(ADC_, DR, __VA_ARGS__)

// --- EXTI ---
#define EXTI_IMR(...)         BITS(EXTI_, IMR, __VA_ARGS__)
#define EXTI_EMR(...)         BITS(EXTI_, EMR, __VA_ARGS__)
#define EXTI_RTSR(...)        BITS(EXTI_, RTSR, __VA_ARGS__)
#define EXTI_FTSR(...)        BITS(EXTI_, FTSR, __VA_ARGS__)
#define EXTI_SWIER(...)       BITS(EXTI_, SWIER, __VA_ARGS__)
#define EXTI_PR(...)          BITS(EXTI_, PR, __VA_ARGS__)

// --- PWR ---
#define PWR_CR(...)           BITS(PWR_, CR, __VA_ARGS__)
#define PWR_CSR(...)          BITS(PWR_, CSR, __VA_ARGS__)

// --- FLASH ---
#define FLASH_ACR(...)        BITS(FLASH_, ACR, __VA_ARGS__)
#define FLASH_KEYR(...)       BITS(FLASH_, KEYR, __VA_ARGS__)
#define FLASH_OPTKEYR(...)    BITS(FLASH_, OPTKEYR, __VA_ARGS__)
#define FLASH_SR(...)         BITS(FLASH_, SR, __VA_ARGS__)
#define FLASH_CR(...)         BITS(FLASH_, CR, __VA_ARGS__)
#define FLASH_AR(...)         BITS(FLASH_, AR, __VA_ARGS__)
#define FLASH_OBR(...)        BITS(FLASH_, OBR, __VA_ARGS__)
#define FLASH_WRPR(...)       BITS(FLASH_, WRPR, __VA_ARGS__)

// --- BKP ---
#define BKP_RTCCR(...)        BITS(BKP_, RTCCR, __VA_ARGS__)
#define BKP_CR(...)           BITS(BKP_, CR, __VA_ARGS__)
#define BKP_CSR(...)          BITS(BKP_, CSR, __VA_ARGS__)

// --- CRC ---
#define CRC_DR(...)           BITS(CRC_, DR, __VA_ARGS__)
#define CRC_IDR(...)          BITS(CRC_, IDR, __VA_ARGS__)
#define CRC_CR(...)           BITS(CRC_, CR, __VA_ARGS__)

// --- WWDG ---
#define WWDG_CR(...)          BITS(WWDG_, CR, __VA_ARGS__)
#define WWDG_CFR(...)         BITS(WWDG_, CFR, __VA_ARGS__)
#define WWDG_SR(...)          BITS(WWDG_, SR, __VA_ARGS__)

// --- IWDG ---
#define IWDG_KR(...)          BITS(IWDG_, KR, __VA_ARGS__)
#define IWDG_PR(...)          BITS(IWDG_, PR, __VA_ARGS__)
#define IWDG_RLR(...)         BITS(IWDG_, RLR, __VA_ARGS__)
#define IWDG_SR(...)          BITS(IWDG_, SR, __VA_ARGS__)

// --- RTC ---
#define RTC_CRH(...)          BITS(RTC_, CRH, __VA_ARGS__)
#define RTC_CRL(...)          BITS(RTC_, CRL, __VA_ARGS__)
#define RTC_PRLH(...)         BITS(RTC_, PRLH, __VA_ARGS__)
#define RTC_PRLL(...)         BITS(RTC_, PRLL, __VA_ARGS__)
#define RTC_DIVH(...)         BITS(RTC_, DIVH, __VA_ARGS__)
#define RTC_DIVL(...)         BITS(RTC_, DIVL, __VA_ARGS__)
#define RTC_CNTH(...)         BITS(RTC_, CNTH, __VA_ARGS__)
#define RTC_CNTL(...)         BITS(RTC_, CNTL, __VA_ARGS__)
#define RTC_ALRH(...)         BITS(RTC_, ALRH, __VA_ARGS__)
#define RTC_ALRL(...)         BITS(RTC_, ALRL, __VA_ARGS__)

// --- DMA Channel Registers (common to all channels) ---
#define DMA_CCR(...)           BITS(DMA_, CCR, __VA_ARGS__)
#define DMA_CNDTR(...)         BITS(DMA_, CNDTR, __VA_ARGS__)
#define DMA_CPAR(...)          BITS(DMA_, CPAR, __VA_ARGS__)
#define DMA_CMAR(...)          BITS(DMA_, CMAR, __VA_ARGS__)

// --- DMA Interrupt and Status Registers ---
#define DMA_ISR(...)           BITS(DMA_, ISR, __VA_ARGS__)
#define DMA_IFCR(...)          BITS(DMA_, IFCR, __VA_ARGS__)


#if defined USE_HSE && USE_HSE != 0
  #define HSE_EN                        YES
#else
  #define HSE_EN                        NO
#endif

#if defined USE_PLL && USE_PLL != 0
  #define PLL_EN                        YES
#else
  #define PLL_EN                        NO
#endif

#if defined USE_LSE && USE_LSE != 0
  #define LSE_EN                        YES
#else
  #define LSE_EN                        NO
#endif

#if defined USE_BTN && USE_BTN != 0
  #define BTN_EN                        YES
  enum {
    BUTTON_1_PRESSED  = (1 << 0),
    BUTTON_2_PRESSED  = (1 << 1),
    BUTTON_1_RELEASED = (1 << 16),
    BUTTON_2_RELEASED = (1 << 17)
  };
#else
  #define BTN_EN                        NO
#endif

#if defined USE_TIM2 && USE_TIM2 != 0
  #define TIM2_EN                       YES
#else
  #define TIM2_EN                       NO
#endif

#if defined USE_DMA && USE_DMA != 0
  #define DMA_EN                        YES
#else
  #define DMA_EN                        NO
#endif

#if defined USE_EXTI && USE_EXTI != 0
  #define EXTI_EN                       YES
#else
  #define EXTI_EN                       NO
#endif

#if defined USE_IWDG && USE_IWDG != 0
  #define IWDG_EN                       YES
#else
  #define IWDG_EN                       NO
#endif

#if defined USE_WWDG && USE_WWDG != 0
  #define WWDG_EN                       YES
  #define WWDG_COUNTER                  0x7F
  #define WWDG_WINDOW                   0x60
#else
  #define WWDG_EN                       NO
#endif

#if defined USE_SWD && USE_SWD != 0
  #define SWD_EN                        YES
#else
  #define SWD_EN                        NO
#endif

#if defined USE_RTC && USE_RTC != 0
  #define RTC_EN                        YES

  typedef struct {
    uint16_t year;
    uint8_t  month;
    uint8_t  day;
    uint8_t  wday;
    uint8_t  hour;
    uint8_t  minute;
    uint8_t  second;
  } time_struct_t;

  #define JD0 2440588

  __STATIC_INLINE unsigned time_to_unixtime(time_struct_t * t) {

    uint8_t a = (14 - t->month) / 12;
    uint16_t y = t->year + 4800 - a;
    uint8_t m = t->month + (12 * a) - 3;
    uint32_t counter = t->day;

    counter += (153 * m + 2) / 5;
    counter += 365 * y;
    counter += y / 4;
    counter -= y / 100;
    counter += y / 400;
    counter -= 32045;
    counter -= JD0;
    counter *= 86400;
    counter += (t->hour * 3600);
    counter += (t->minute * 60);
    counter += (t->second);

    return counter;
  }


  __STATIC_INLINE void unixtime_to_time(uint32_t utime, time_struct_t * t) {

    uint32_t ace, b, d, m;

    ace = (utime / 86400) + 32044 + JD0;
    b = (4 * ace + 3) / 146097;
    ace = ace - ((146097 * b) / 4);
    d = (4 * ace + 3) / 1461;
    ace = ace - ((1461 * d) / 4);
    m = (5 * ace + 2) / 153;
    t->day = (uint8_t)(ace - ((153 * m + 2) / 5) + 1);
    t->month = (uint8_t) (m + 3 - (12 * (m / 10)));
    t->year = (uint16_t) (100 * b + d - 4800 + (m / 10));
    t->hour = (utime / 3600) % 24;
    t->minute = (utime / 60) % 60;
    t->second = (utime % 60);
  }


  __STATIC_INLINE unsigned rtc_read_counter(void) {
    unsigned a = RTC->CNTH, b = RTC->CNTL, c = RTC->CNTH;
    if (a != c) {
      a = c;
      b = RTC->CNTL;
    }
    a = (a << 16U) | b;
    return a;
  }

  __STATIC_INLINE void rtc_set_alarm(unsigned alarm_time) {

    unsigned apb1enr = RCC->APB1ENR, pwr_cr_dbp;

    SET_REG_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
    SET_REG_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);

    pwr_cr_dbp = READ_REG_BIT(PWR->CR, PWR_CR_DBP);           /* Save protection bit status         */
    SET_REG_BIT(PWR->CR, PWR_CR_DBP);                         /* Disable Backup Domain Protection   */

    while (!READ_REG_BIT(RTC->CRL, RTC_CRL_RTOFF)) {  }       /* Wait if write op is still ongoing  */

    SET_REG_BIT(RTC->CRL, RTC_CRL_CNF);                       /* Enter configuration mode           */

    RTC->ALRH = (unsigned short)(alarm_time >> 16);           /* Set RTC Alarm value MS half-word   */
    RTC->ALRL = (unsigned short)(alarm_time & RTC_ALRL_RTC_ALR); /* Set RTC Alarm value LS half-word*/

    SET_REG_BIT(RTC->CRH, RTC_CRH_ALRIE);                     /* Alarm interrupt enable             */
    CLEAR_REG_BIT(RTC->CRL, RTC_CRL_CNF);                     /* The write operation only executes  */
                                                              /* when the CNF bit is cleared; it    */
                                                              /* takes at least three RTCCLK cycles */
                                                              /* to complete.                       */

    while (!READ_REG_BIT(RTC->CRL, RTC_CRL_RTOFF)) {  }       /* Wait if write op is still ongoing  */

    WRITE_REG_BIT(PWR->CR, PWR_CR_DBP, pwr_cr_dbp);
    RCC->APB1ENR = apb1enr;

  } /* rtc_set_alarm() */


  __STATIC_INLINE void rtc_set_counter(unsigned counter) {

    unsigned apb1enr = RCC->APB1ENR, pwr_cr_dbp;

    SET_REG_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
    SET_REG_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);

    pwr_cr_dbp = READ_REG_BIT(PWR->CR, PWR_CR_DBP);           /* Save protection bit status         */
    SET_REG_BIT(PWR->CR, PWR_CR_DBP);                         /* Disable Backup Domain Protection   */

    while (!READ_REG_BIT(RTC->CRL, RTC_CRL_RTOFF)) {  }       /* Wait if write op is still ongoing  */

    SET_REG_BIT(RTC->CRL, RTC_CRL_CNF);                       /* Enter configuration mode           */

    RTC->CNTH = (unsigned short)(counter >> 16);              /* Set RTC counter MSB word           */
    RTC->CNTL = (unsigned short)(counter & RTC_CNTL_RTC_CNT); /* Set RTC counter LSB word           */

    CLEAR_REG_BIT(RTC->CRL, RTC_CRL_CNF);                     /* The write operation only executes  */
                                                              /* when the CNF bit is cleared; it    */
                                                              /* takes at least three RTCCLK cycles */
                                                              /* to complete.                       */

    while (!READ_REG_BIT(RTC->CRL, RTC_CRL_RTOFF)) {  }       /* Wait if write op is still ongoing  */

    WRITE_REG_BIT(PWR->CR, PWR_CR_DBP, pwr_cr_dbp);
    RCC->APB1ENR = apb1enr;
  } /* rtc_set_counter() */
#else
  #define RTC_EN                        NO
#endif

#if defined USE_ADC && USE_ADC != 0

  #define ADC_EN                        YES

  #define ADC_CHANNEL_0                 0x00000000U
  #define ADC_CHANNEL_1                 (                                                                        ADC_CR1_AWDCH_0)
  #define ADC_CHANNEL_2                 (                                                      ADC_CR1_AWDCH_1                  )
  #define ADC_CHANNEL_3                 (                                                      ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
  #define ADC_CHANNEL_4                 (                                    ADC_CR1_AWDCH_2                                    )
  #define ADC_CHANNEL_5                 (                                    ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)
  #define ADC_CHANNEL_6                 (                                    ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )
  #define ADC_CHANNEL_7                 (                                    ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
  #define ADC_CHANNEL_8                 (                  ADC_CR1_AWDCH_3                                                      )
  #define ADC_CHANNEL_9                 (                  ADC_CR1_AWDCH_3                                     | ADC_CR1_AWDCH_0)
  #define ADC_CHANNEL_10                (                  ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1                  )
  #define ADC_CHANNEL_11                (                  ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
  #define ADC_CHANNEL_12                (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                                    )
  #define ADC_CHANNEL_13                (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)
  #define ADC_CHANNEL_14                (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )
  #define ADC_CHANNEL_15                (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
  #define ADC_CHANNEL_16                (ADC_CR1_AWDCH_4                                                                        )
  #define ADC_CHANNEL_17                (ADC_CR1_AWDCH_4                                                       | ADC_CR1_AWDCH_0)

  #define ADC_SAMPLING_TIME_1_5         (0x00000000U                                           ) /* Sampling time   1.5 ADC clock cycle  */
  #define ADC_SAMPLING_TIME_7_5         (                                      ADC_SMPR2_SMP0_0) /* Sampling time   7.5 ADC clock cycles */
  #define ADC_SAMPLING_TIME_13_5        (                   ADC_SMPR2_SMP0_1                   ) /* Sampling time  13.5 ADC clock cycles */
  #define ADC_SAMPLING_TIME_28_5        (                   ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /* Sampling time  28.5 ADC clock cycles */
  #define ADC_SAMPLING_TIME_41_5        (ADC_SMPR2_SMP0_2                                      ) /* Sampling time  41.5 ADC clock cycles */
  #define ADC_SAMPLING_TIME_55_5        (ADC_SMPR2_SMP0_2 |                    ADC_SMPR2_SMP0_0) /* Sampling time  55.5 ADC clock cycles */
  #define ADC_SAMPLING_TIME_71_5        (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1                   ) /* Sampling time  71.5 ADC clock cycles */
  #define ADC_SAMPLING_TIME_239_5       (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /* Sampling time 239.5 ADC clock cycles */

  #define _ADC_SQR1(SEQ_NUM, CH_NUM)    ((ADC_CHANNEL_ ## CH_NUM << ADC_SQR1_SQ ## SEQ_NUM ##_Pos) & ADC_SQR1_SQ ## SEQ_NUM)
  #define _ADC_SQR2(SEQ_NUM, CH_NUM)    ((ADC_CHANNEL_ ## CH_NUM << ADC_SQR2_SQ ## SEQ_NUM ##_Pos) & ADC_SQR2_SQ ## SEQ_NUM)
  #define _ADC_SQR3(SEQ_NUM, CH_NUM)    ((ADC_CHANNEL_ ## CH_NUM << ADC_SQR3_SQ ## SEQ_NUM ##_Pos) & ADC_SQR3_SQ ## SEQ_NUM)
  #define _ADC_SQR1_LEN(LEN)            (((uint32_t)((LEN) - 1) << ADC_SQR1_L_Pos) & ADC_SQR1_L)

  #define _ADC_SMPR1(SEQ_NUM, CYCLES)   ((ADC_SAMPLING_TIME_ ## CYCLES ## _5 << ADC_SMPR1_SMP ## SEQ_NUM ## _Pos) & ADC_SMPR1_SMP ## SEQ_NUM)
  #define _ADC_SMPR2(SEQ_NUM, CYCLES)   ((ADC_SAMPLING_TIME_ ## CYCLES ## _5 << ADC_SMPR2_SMP ## SEQ_NUM ## _Pos) & ADC_SMPR2_SMP ## SEQ_NUM)


  __STATIC_INLINE unsigned adc_get_bit(void) {
    while (!READ_REG_BIT(ADC1->SR, ADC_SR_EOC)) {
    }
    return READ_REG_BIT(ADC1->DR, 1);
  }


  __STATIC_INLINE unsigned adc_get_random_bit(void) {
    unsigned a;
    do {
      a = adc_get_bit();
    } while (a == adc_get_bit());
    return a;
  }

  __STATIC_INLINE unsigned adc_get_average(unsigned count) {
    unsigned average = 0;
    for(unsigned i = 0; i < count; i++) {

      while (!READ_REG_BIT(ADC1->SR, ADC_SR_EOC)) { }
      average += ADC1->DR;

      #if WWDG_EN
        if ((WWDG->CR & WWDG_CR_T) < WWDG_WINDOW) {
          WWDG->CR = WWDG_COUNTER; /* Reset WWDG */
        }
      #endif
    }
    return average / count;
  }


  __STATIC_INLINE void get_adc_internals(short *t, unsigned short *v) {

    enum { ADC_SAMPLE_COUNT = 128 + (4096 - 128) * PLL_EN };

    unsigned temp_data, vcc_data, vcc;

    temp_data = adc_get_average(ADC_SAMPLE_COUNT);
    CLEAR_REG_BIT(ADC1->CR2, ADC_CR2_ADON);
    while (READ_REG_BIT(ADC1->CR2, ADC_CR2_ADON)) { }

    ADC1->SQR3 = _ADC_SQR3(1, 17);
    SET_REG_BIT(ADC1->CR2, ADC_CR2_ADON);
    SET_REG_BIT(ADC1->CR2, ADC_CR2_ADON);

    vcc_data = adc_get_average(ADC_SAMPLE_COUNT);
    CLEAR_REG_BIT(ADC1->CR2, ADC_CR2_ADON);
    while (READ_REG_BIT(ADC1->CR2, ADC_CR2_ADON)) { }

    ADC1->SQR3 = _ADC_SQR3(1, 16);
    SET_REG_BIT(ADC1->CR2, ADC_CR2_ADON);
    SET_REG_BIT(ADC1->CR2, ADC_CR2_ADON);

    vcc = 1200UL * 4095UL / vcc_data;
    {
      int temp = temp_data * vcc / 4095L;
      temp = ((1430L - temp) * 10L / 43L) + 25L;
      if (t != NULL) *t = (short) temp;
      if (v != NULL) *v = (unsigned short) vcc;
    }
  }

#else
  #define ADC_EN                        NO
#endif

#if defined USE_USART && USE_USART != 0
  #define USART_EN                      YES
  #define BAUDRATE 115200
#else
  #define USART_EN                      NO
#endif

#if defined USE_I2C && USE_I2C != 0
  #define I2C_EN                        YES
  #define I2C_SPEED_STANDARD            100000
  #define I2C_SPEED_FAST                400000

  #if !0
    #define _I2C_CCR                    (((APB1_CLK / I2C_SPEED_STANDARD / 2) & I2C_CCR_CCR) < 4U) ? 4U : APB1_CLK / I2C_SPEED_STANDARD / 2
    #define _I2C_TRISE                  APB1_CLK / 1000000 + 1
  #else
    #define _I2C_CCR                    (((APB1_CLK / I2C_SPEED_FAST / 3) & I2C_CCR_CCR) == 0U) ? 1U : APB1_CLK / I2C_SPEED_FAST / 3
    #define _I2C_TRISE                  3 * APB1_CLK / 10000000 + 1
  #endif

#else
  #define I2C_EN                        NO
#endif

#if defined USE_SPI && USE_SPI != 0

  #define SPI_EN                        YES

  __STATIC_INLINE char spi_xfer(char d) {
    while(!READ_REG_BIT(SPI1->SR, SPI_SR_TXE))  { /* Wait for the TX buffer to become empty    */ }
    *((__IO char *)&SPI1->DR) = d;
    while(!READ_REG_BIT(SPI1->SR, SPI_SR_RXNE)) { /* Poll RX status register for received data */ }
    return *(__IO char *)&SPI1->DR;
  }

  #define CS_PORT                       GPIOA
  #define CS_PIN                        4
  #define CS(STATE)                     CS_PORT->BSRR = (1UL << ((!STATE) * 16 + CS_PIN))
  #define CS_LOW()                      CS(0)
  #define CS_HIGH()                     CS(1)

#else
  #define SPI_EN                        NO
#endif

#if defined USE_CRC && USE_CRC != 0
  #define CRC_EN                        YES
  __STATIC_INLINE unsigned crc32_zlib(const unsigned *data, unsigned short cnt) {

    unsigned i, result;

    CRC->CR = CRC_CR_RESET;

    for (i = 0; i < (cnt / 4); i++) CRC->DR = __RBIT(data[i]);

    result = __RBIT(CRC->DR);
    cnt = (cnt % 4) * 8;
    if (cnt) {
      CRC->DR = CRC->DR;
      CRC->DR = __RBIT((data[i] & (0xFFFFFFFF >> (32 - cnt))) ^ result) >> (32 - cnt);
      result = (result >> cnt) ^ __RBIT(CRC->DR);
    }
    return ~result;
  }
#else
  #define CRC_EN                        NO
#endif

#if defined USE_RNG && USE_RNG != 0

  #define RNG_EN                        YES

    unsigned rnd(void);
    void srnd(unsigned);

  __STATIC_INLINE unsigned prnd(void) {

    for (unsigned i = 0; i < 0x2000; i++) {
      CRC->DR = ((unsigned *) APB1PERIPH_BASE)[i];
    }

    for (unsigned i = 0; i < 0x1000; i++) {
      CRC->DR = ((unsigned *) APB2PERIPH_BASE)[i];
    }

    for (unsigned i = 0; i < 0x100; i++) {
      CRC->DR = ((unsigned *) AHBPERIPH_BASE)[i];
    }

    for (unsigned i = 0; i < 0x4000; i++) {
      CRC->DR = ((unsigned *) FLASH_BASE)[i];
    }

    for (unsigned i = 0; i < 0x1000; i++) {
      CRC->DR = ((unsigned *) SRAM_BASE)[i];
    }

    for (unsigned i = 0; i < 0x40000; i++) {
      CRC->DR = ((unsigned *) ITM_BASE)[i];
    }

    for (unsigned i = 0; i < 0x204; i++) {
      CRC->DR = ((unsigned *) 0x1FFFF000)[i];
    }

    return CRC->DR;
  }

#else
  #define RNG_EN                        NO
#endif

#if defined USE_FLASH && USE_FLASH != 0

  #define FLASH_EN                      YES

 /**
   * @brief   Flash programming routines for STM32F103 (auto-detects C4/C6/C8/CB)
   * 
   * @details Implements page erase, half-word programming, and verification
   *          according to PM0075 (STM32F10xxx Flash programming manual).
   *          Automatically detects Flash size at runtime.
   * 
   * @note    Optimizations applied:
   *          - Countdown loops with unsigned counters
   *          - do-while loops where iteration count is known
   *          - Loop unrolling (4x) for verification functions
   *          - Pre-decrement in loop conditions (--n != 0)
   *          - __restrict pointers for better code generation
   *          - Direct register access instead of macros
   *          - Interrupt disable/enable with PRIMASK save/restore
   * 
   * @note    Supported hardware (auto-detected):
   *          - STM32F103C4: 16KB Flash, 16 pages Г— 1KB
   *          - STM32F103C6: 32KB Flash, 32 pages Г— 1KB
   *          - STM32F103C8: 64KB Flash, 64 pages Г— 1KB
   *          - STM32F103CB: 128KB Flash, 128 pages Г— 1KB
   *          - Page erase time: ~40ms
   *          - Half-word programming time: ~50Вµs
   * 
   * @note    C8 Quirk Mode (FLASH_C8_QUIRK):
   *          Many STM32F103C8T6 chips (especially "Blue Pill" boards) actually
   *          have 128KB Flash instead of the specified 64KB. When FLASH_C8_QUIRK
   *          is defined, the code will use the last page at 0x0801FC00 for C8
   *          chips, allowing access to the full 128KB.
   * 
   * @warning According to page 25 of RM0008, Flash operations require HSI clock
   *          enabled and disable interrupts to prevent CPU stalls when attempting
   *          to fetch instructions from Flash during write/erase operations.
   * 
   * @author  a5021
   * @date    October 2025
   */
  
  /* Configuration: Enable C8 quirk mode for 128KB Flash on C8T6 chips */
  /* Uncomment the line below to enable quirk mode for "Blue Pill" boards */
  /* #define FLASH_C8_QUIRK 1 */
  
  /* Flash size register address (factory-programmed) */
  #define FLASH_SIZE_REG      ((uint16_t*)0x1FFFF7E0)  /**< Flash size in KB */
  
  /* Page size constant - always 1KB for STM32F103 (all variants) */
  #define FLASH_PAGE_SIZE       0x00000400  /**< 1KB page size (1024 bytes) */
  
  /* Error codes (can be combined as bitmask) */
  #define FLASH_ERROR_WRITE_PROT      0x01  /**< Write protection error */
  #define FLASH_ERROR_WRITE           0x02  /**< Programming error */
  #define FLASH_ERROR_ERASE           0x04  /**< Erase verification failed */
  #define FLASH_ERROR_UNKNOWN         0x08  /**< Unknown/timeout error */
  #define FLASH_ERROR_HSI             0x10  /**< HSI clock not enabled */
  #define FLASH_ERROR_ALIGN           0x20  /**< Alignment error (address or length) */
  #define FLASH_ERROR_SIZE            0x40  /**< Data size exceeds page size */
  
  /**
   * @brief   Get Flash size in KB from factory-programmed register
   * @return  Flash size in kilobytes (16, 32, 64, or 128)
   * 
   * @note    This reads the factory-programmed register at 0x1FFFF7E0.
   *          Returns: 16 for C4, 32 for C6, 64 for C8, 128 for CB.
   *          Note: Many C8 chips report 64KB but actually have 128KB.
   */
  __STATIC_FORCEINLINE uint16_t flash_get_size_kb(void) {
    return *FLASH_SIZE_REG;
  }
  
  /**
   * @brief   Get last Flash page address based on detected Flash size
   * @return  Address of the last page (suitable for data storage)
   * 
   * @details Calculates last page address dynamically:
   *          - STM32F103C4 (16KB):  0x08003C00 (page 15)
   *          - STM32F103C6 (32KB):  0x08007C00 (page 31)
   *          - STM32F103C8 (64KB):  0x0800FC00 (page 63)
   *                        [quirk]: 0x0801FC00 (page 127, if FLASH_C8_QUIRK defined)
   *          - STM32F103CB (128KB): 0x0801FC00 (page 127)
   * 
   * @note    When FLASH_C8_QUIRK is defined, C8 chips use the same last page
   *          address as CB (0x0801FC00) to access the extra 64KB of Flash that
   *          many C8 chips actually have.
   */
  __STATIC_FORCEINLINE uint32_t flash_get_last_page_addr(void) {
    const uint16_t flash_kb = flash_get_size_kb();
    
  #ifdef FLASH_C8_QUIRK
    /* Quirk mode: treat C8 (64KB) as CB (128KB) for last page calculation */
    if (flash_kb == 64) {
      return 0x0801FC00UL;  /* Use CB's last page address */
    }
  #endif
    
    return (0x08000000UL + (flash_kb << 10) - FLASH_PAGE_SIZE);
  }
  
  /**
   * @brief   Read Flash status register and return error flags
   * @return  Error bitmask (0 = no error, combination of FLASH_ERROR_xxx)
   * 
   * @details Reads FLASH->SR once and tests both error bits:
   *          - FLASH_SR_WRPRTERR: Write protection error
   *          - FLASH_SR_PGERR: Programming sequence error
   * 
   * @note    Single register read minimizes bus access overhead
   */
  __STATIC_FORCEINLINE unsigned flash_get_err(void) {
    const uint32_t sr = FLASH->SR;
    return ((sr & FLASH_SR_WRPRTERR) ? FLASH_ERROR_WRITE_PROT : 0) |
           ((sr & FLASH_SR_PGERR) ? FLASH_ERROR_WRITE : 0);
  }
  
  /**
   * @brief   Verify entire Flash page is blank (erased to 0xFFFFFFFF)
   * @param   addr  Start address of page to verify (must be page-aligned)
   * @return  0 on success, FLASH_ERROR_ERASE if page not blank
   * 
   * @details Checks entire FLASH_PAGE_SIZE (1024 bytes = 256 words) as 32-bit
   *          words for optimal performance.
   * 
   * @note    Optimizations applied:
   *          - Countdown loop (free comparison with zero)
   *          - Unsigned counter with i!=0 condition
   *          - do-while loop (guaranteed at least one iteration)
   *          - Unrolled by 4 (256 words в†’ 64 iterations)
   *          - FLASH_PAGE_SIZE is always multiple of 16 bytes
   */
  __STATIC_FORCEINLINE unsigned flash_verify_blank(uint32_t addr) {
    const __IO uint32_t *__restrict p = (const __IO uint32_t *)addr;
    unsigned i = FLASH_PAGE_SIZE >> 2;  /* 256 words, countdown */
    
    /* Unroll by 4 to reduce loop overhead */
    do {
      if (p[0] != 0xFFFFFFFFU) return FLASH_ERROR_ERASE;
      if (p[1] != 0xFFFFFFFFU) return FLASH_ERROR_ERASE;
      if (p[2] != 0xFFFFFFFFU) return FLASH_ERROR_ERASE;
      if (p[3] != 0xFFFFFFFFU) return FLASH_ERROR_ERASE;
      p += 4;
      i -= 4;
    } while (i != 0);  /* Countdown to zero */
    
    return 0;
  }
  
  /**
   * @brief   Verify programmed Flash data matches source buffer
   * @param   addr  Flash address to verify
   * @param   data  Expected data buffer (half-word array)
   * @param   len   Data length in bytes (must be even)
   * @return  0 on success, FLASH_ERROR_WRITE if mismatch detected
   * 
   * @details Compares Flash content with source buffer half-word by half-word.
   * 
   * @note    Optimizations applied:
   *          - Countdown loop with unsigned counter
   *          - Unrolled by 4 for main loop
   *          - Handles remaining 1-3 half-words separately
   *          - __restrict pointers allow better optimization
   */
  __STATIC_FORCEINLINE unsigned flash_verify_data(uint32_t addr, 
                                                   const uint16_t *__restrict data, 
                                                   uint16_t len) {
    const __IO uint16_t *__restrict p = (const __IO uint16_t *)addr;
    unsigned n = len >> 1;  /* Half-words count */
    
    /* Process 4 half-words at a time (unroll by 4) */
    while (n >= 4) {
      if (p[0] != data[0]) return FLASH_ERROR_WRITE;
      if (p[1] != data[1]) return FLASH_ERROR_WRITE;
      if (p[2] != data[2]) return FLASH_ERROR_WRITE;
      if (p[3] != data[3]) return FLASH_ERROR_WRITE;
      p += 4;
      data += 4;
      n -= 4;
    }
    
    /* Handle remaining 1-3 half-words (countdown loop) */
    if (n != 0) {
      do {
        if (*p++ != *data++) return FLASH_ERROR_WRITE;
      } while (--n != 0);
    }
    
    return 0;
  }
  
  /**
   * @brief   Erase Flash page and verify blank
   * @param   addr  Start address of page to erase (must be page-aligned)
   * @return  0 on success, error code on failure
   * 
   * @details Performs Flash page erase operation according to PM0075:
   *          1. Clear previous status flags
   *          2. Wait for any pending operation to complete (BSY=0)
   *          3. Set PER (Page Erase) bit in FLASH_CR
   *          4. Write target page address to FLASH_AR
   *          5. Set STRT bit to start erase (with interrupts disabled)
   *          6. Wait for BSY=0 (erase completes in ~40ms)
   *          7. Check for errors in FLASH_SR
   *          8. Clear PER bit and status flags
   *          9. Verify entire page is blank (0xFFFFFFFF)
   * 
   * @warning Interrupts are disabled during erase operation to prevent CPU
   *          from attempting to fetch instructions from Flash, which would
   *          cause a hard fault. Maximum interrupt latency: ~40ms.
   * 
   * @note    Uses PRIMASK save/restore to preserve caller's interrupt state.
   *          Assumes HSI clock is already verified by caller.
   */
  __STATIC_INLINE unsigned flash_erase_page(uint32_t addr) {
    /* Clear previous operation flags */
    FLASH->SR = FLASH_SR_EOP | FLASH_SR_PGERR | FLASH_SR_WRPRTERR;
    while (FLASH->SR & FLASH_SR_BSY);  /* Wait until ready */
    
    /* Setup page erase */
    FLASH->CR |= FLASH_CR_PER;         /* Enable page erase mode */
    FLASH->AR = addr;                  /* Set target page address */
    
    /* Start erase with interrupts disabled */
    const uint32_t primask = __get_PRIMASK();
    __disable_irq();
    
    FLASH->CR |= FLASH_CR_STRT;        /* Start erase operation */
    while (FLASH->SR & FLASH_SR_BSY);  /* Wait ~40ms until complete */
    const unsigned st = flash_get_err();
    
    __set_PRIMASK(primask);            /* Restore interrupt state */
    
    /* Cleanup */
    FLASH->CR &= ~FLASH_CR_PER;        /* Disable page erase mode */
    FLASH->SR = FLASH_SR_EOP | FLASH_SR_PGERR | FLASH_SR_WRPRTERR;
    
    /* Verify entire page is blank */
    return st ? st : flash_verify_blank(addr);
  }
  
  /**
   * @brief   Program half-words to Flash and verify
   * @param   addr  Flash destination address (must be half-word aligned)
   * @param   src   Source data buffer (half-word array)
   * @param   len   Data length in bytes (must be even)
   * @return  0 on success, error code on failure
   * 
   * @details Performs Flash half-word programming according to PM0075:
   *          1. Validate alignment (address and length must be even)
   *          2. Clear previous status flags
   *          3. Wait for any pending operation (BSY=0)
   *          4. Set PG (Programming) bit in FLASH_CR
   *          5. For each half-word (with interrupts disabled):
   *             a. Write half-word to Flash address
   *             b. Wait for BSY=0 (~50Вµs per half-word)
   *             c. Check for errors
   *          6. Clear PG bit and status flags
   *          7. Verify programmed data matches source
   * 
   * @note    Loop optimizations:
   *          - Countdown loop with unsigned counter
   *          - Pre-decrement in condition (--n != 0) for optimal ARM code
   *          - No unrolling (50Вµs hardware wait dominates loop overhead)
   * 
   * @warning - Flash must be erased (0xFFFF) before programming
   *          - Interrupts disabled during writes (~50Вµs per half-word)
   *          - Cannot program same address twice without erase
   *          - CPU cannot fetch instructions from Flash during programming
   *          - Assumes HSI clock is already verified by caller
   */
  __STATIC_INLINE unsigned flash_program(uint32_t addr, 
                                          const uint16_t *__restrict src, 
                                          uint16_t len) {
    /* Validate alignment */
    if ((len & 1u) | (addr & 1u)) return FLASH_ERROR_ALIGN;
    
    __IO uint16_t *__restrict p = (__IO uint16_t *)addr;
    unsigned n = len >> 1;  /* Half-words count (unsigned, countdown) */
    unsigned st = 0;
    
    /* Prepare for programming */
    FLASH->SR = FLASH_SR_EOP | FLASH_SR_PGERR | FLASH_SR_WRPRTERR;
    while (FLASH->SR & FLASH_SR_BSY);
    
    FLASH->CR |= FLASH_CR_PG;          /* Enable programming mode */
    
    /* Program half-words with interrupts disabled */
    const uint32_t primask = __get_PRIMASK();
    __disable_irq();
    
    /* Countdown loop: write each half-word to Flash */
    do {
      *p++ = *src++;                   /* Write triggers Flash operation */
      while (FLASH->SR & FLASH_SR_BSY); /* Wait ~50Вµs per half-word */
      if ((st = flash_get_err()) != 0u) break;
    } while (--n != 0);                /* Pre-decrement, compare with zero */
    
    __set_PRIMASK(primask);            /* Restore interrupt state */
    
    /* Cleanup */
    FLASH->CR &= ~FLASH_CR_PG;         /* Disable programming mode */
    FLASH->SR = FLASH_SR_EOP | FLASH_SR_PGERR | FLASH_SR_WRPRTERR;
    
    /* Verify programmed data */
    return st ? st : flash_verify_data(addr, src, len);
  }
  
  /**
   * @brief   Erase and program Flash data area (auto-detects last page)
   * @param   src   Source data buffer (half-word array)
   * @param   len   Data length in bytes (must be even, max 1024 bytes)
   * @return  0 on success, error code on failure
   * 
   * @details High-level Flash write operation that performs:
   *          1. Validate alignment (length must be even)
   *          2. Validate data size (must not exceed page size)
   *          3. Detect Flash size (16/32/64/128KB) from factory register
   *          4. Calculate last page address automatically
   *          5. Check HSI clock is enabled (required per RM0008 page 25)
   *          6. Unlock Flash controller if locked
   *          7. Erase target page (last page)
   *          8. Program new data if erase successful
   *          9. Re-lock Flash controller for safety
   * 
   * @note    Execution time breakdown:
   *          - Page erase: ~40ms
   *          - Programming: (len/2) Г— 50Вµs
   *          - Verification: (len/2) Г— ~1Вµs
   *          - Example for 1KB: 40ms + 25ms + 0.5ms ≈ 65ms
   * 
   * @note    Automatic detection (works on all variants):
   *          - STM32F103C4 (16KB):  Uses page at 0x08003C00
   *          - STM32F103C6 (32KB):  Uses page at 0x08007C00
   *          - STM32F103C8 (64KB):  Uses page at 0x0800FC00
   *                       [quirk]:  Uses page at 0x0801FC00 (with FLASH_C8_QUIRK)
   *          - STM32F103CB (128KB): Uses page at 0x0801FC00
   * 
   * @note    C8 Quirk Mode:
   *          When FLASH_C8_QUIRK is defined, C8 chips will use the last page
   *          at 0x0801FC00 (same as CB) to access the full 128KB that many
   *          "Blue Pill" boards actually have. This is safe because:
   *          - If chip has 128KB: Works perfectly, accesses upper memory
   *          - If chip has only 64KB: Flash operation will fail with error
   * 
   * @warning - This function blocks for the entire operation duration
   *          - Interrupts disabled during erase (~40ms) and program operations
   *          - Maximum total interrupt latency: ~65ms for 1KB page
   *          - Flash controller remains locked after completion
   *          - HSI clock must be enabled before calling this function
   *          - Data length must be even (half-word aligned)
   *          - Data size must not exceed FLASH_PAGE_SIZE (1024 bytes)
   * 
   * @example Basic usage (works on C4/C6/C8/CB):
   * @code
   * // Enable quirk mode in your project (optional):
   * // #define FLASH_C8_QUIRK 1
   * 
   * // HSI is typically enabled by default in SystemInit()
   * 
   * // Union for test string
   * union {
   *     char str[64];
   *     uint16_t halfwords[32];
   * } test_data = {
   *     .str = "Just a test string to write to the flash page."
   * };
   * 
   * unsigned len = (strlen(test_data.str) + 2) & ~1u;  // Round up to even
   * unsigned status = write2flash(test_data.halfwords, len);
   * 
   * if (status == 0) {
   *     // Success: data written and verified
   *     // Read back from auto-detected address
   *     const char *flash_str = (const char *)flash_get_last_page_addr();
   *     if (strcmp(flash_str, test_data.str) == 0) {
   *         // Perfect match!
   *     }
   * } else {
   *     // Error handling
   *     if (status & FLASH_ERROR_HSI) { }        // HSI not enabled
   *     if (status & FLASH_ERROR_SIZE) { }       // Data too large
   *     if (status & FLASH_ERROR_ALIGN) { }      // Alignment error
   *     if (status & FLASH_ERROR_WRITE_PROT) { } // Write protected
   *     if (status & FLASH_ERROR_ERASE) { }      // Erase failed
   *     if (status & FLASH_ERROR_WRITE) { }      // Write failed
   * }
   * @endcode
   */
  __STATIC_INLINE unsigned write2flash(uint16_t src[], uint16_t len) {
    /* Validate alignment (length must be even) */
    if (len & 1u) {
      return FLASH_ERROR_ALIGN;
    }
    
    /* Validate data size does not exceed page size */
    if (len > FLASH_PAGE_SIZE) {
      return FLASH_ERROR_SIZE;
    }
    
    /* Check HSI is enabled (required per RM0008 page 25) */
    if (!(RCC->CR & RCC_CR_HSIRDY)) {
      return FLASH_ERROR_HSI;
    }
    
    /* Auto-detect last page address based on Flash size */
    const uint32_t flash_data_addr = flash_get_last_page_addr();
    
    /* Unlock Flash if locked */
    if (FLASH->CR & FLASH_CR_LOCK) {
      FLASH->KEYR = FLASH_KEY1;        /* Unlock sequence */
      FLASH->KEYR = FLASH_KEY2;
    }
    
    /* Erase page */
    unsigned st = flash_erase_page(flash_data_addr);
    
    /* Program only if erase succeeded */
    if (st == 0u) {
      st = flash_program(flash_data_addr, src, len);
    }
    
    /* Re-lock Flash */
    FLASH->CR |= FLASH_CR_LOCK;
    
    return st;
  }

  #define OB_RDP_LEVEL_0            ((uint8_t)0xA5)
  #define OB_RDP_LEVEL_1            ((uint8_t)0x00)

  __STATIC_INLINE void __NO_RETURN lock_firmware(uint8_t *ud_0, uint8_t *ud_1) {

    while (READ_REG_BIT(FLASH->SR, FLASH_SR_BSY)) {/* */}     /* Wait till no operation is on going */

    FLASH->KEYR = FLASH_KEY1;                                 /* Perform FLASH unlock sequence      */
    FLASH->KEYR = FLASH_KEY2;

    FLASH->OPTKEYR = FLASH_OPTKEY1;                           /* Perform OPT BYTE unlock sequence   */
    FLASH->OPTKEYR = FLASH_OPTKEY2;

    SET_REG_BIT(FLASH->CR, FLASH_CR_OPTER);                   /* Enable OPT BYTE erasing operation  */
    SET_REG_BIT(FLASH->CR, FLASH_CR_STRT);                    /* Start erasing..                    */

    while (READ_REG_BIT(FLASH->SR, FLASH_SR_BSY)) {/* */}     /* Wait till no operation is on going */

    CLEAR_REG_BIT(FLASH->CR, FLASH_CR_OPTER);                 /* Disable OPT BYTE erase operation   */
    SET_REG_BIT(FLASH->CR, FLASH_CR_OPTPG);                   /* Enable OPT BYTE programming op.    */

    if (ud_0 != NULL) {                                       /* if user byte #0 is passed          */
      OB->Data0 = *ud_0;                                      /* write it to OPT BYTE               */
      while (!READ_REG_BIT(FLASH->SR, FLASH_SR_EOP)) {/* */}  /* wait until write op completes      */
      SET_REG_BIT(FLASH->SR, FLASH_SR_EOP);                   /* clear OPERATION COMPLETE flag      */
    }

    if (ud_1 != NULL) {                                       /* if user byte #0 is passed          */
      OB->Data1 = *ud_1;                                      /* write it to OPT BYTE               */
      while (!READ_REG_BIT(FLASH->SR, FLASH_SR_EOP)) {/* */}  /* wait until write op completes      */
      SET_REG_BIT(FLASH->SR, FLASH_SR_EOP);                   /* clear OPERATION COMPLETE flag      */
    }
                                                                                                    /*
      For medium-density devices, one bit of the user option bytes WRPx is used to
      protect 4 pages of 1 Kbyte in main memory block.
        0: Write protection active
        1: Write protection not active
      In total, four user option bytes are used to protect the 128-Kbyte main Flash
      memory.
      WRP0: Write-protects pages 0 to 31
      WRP1: Write-protects pages 32 to 63
      WRP2: Write-protects pages 64 to 95
      WRP3: Write-protects pages 96 to 127
                                                                                                    */
    OB->WRP0 = (uint16_t)0x00;                                /* write-protect pages 0 to 31        */
    while (!READ_REG_BIT(FLASH->SR, FLASH_SR_EOP)) {/* */}    /* wait until write op completes      */
    SET_REG_BIT(FLASH->SR, FLASH_SR_EOP);                     /* clear OPERATION COMPLETE flag      */

    OB->WRP1 = (uint16_t)0x00;                                /* write-protect pages 32 to 63       */
    while (!READ_REG_BIT(FLASH->SR, FLASH_SR_EOP)) {/* */}    /* wait until write op completes      */
    SET_REG_BIT(FLASH->SR, FLASH_SR_EOP);                     /* clear OPERATION COMPLETE flag      */

    OB->WRP2 = (uint16_t)0x00;                                /* write-protect pages 64 to 95       */
    while (!READ_REG_BIT(FLASH->SR, FLASH_SR_EOP)) {/* */}    /* wait until write op completes      */
    SET_REG_BIT(FLASH->SR, FLASH_SR_EOP);                     /* clear OPERATION COMPLETE flag      */

    OB->WRP3 = (uint16_t)0x80;                                /* write-protect pages 96 to 127      */
    while (!READ_REG_BIT(FLASH->SR, FLASH_SR_EOP)) {/* */}    /* wait until write op completes      */
    SET_REG_BIT(FLASH->SR, FLASH_SR_EOP);                     /* clear OPERATION COMPLETE flag      */

    OB->RDP = OB_RDP_LEVEL_1;                                 /* Enable read out protection         */
    while (!READ_REG_BIT(FLASH->SR, FLASH_SR_EOP)) {/* */}    /* wait until write op completes      */
    SET_REG_BIT(FLASH->SR, FLASH_SR_EOP);                     /* clear OPERATION COMPLETE flag      */

    CLEAR_REG_BIT(FLASH->CR, FLASH_CR_OPTPG);                 /* Disable OPT BYTE programming op.   */
    while (READ_REG_BIT(FLASH->SR, FLASH_SR_BSY)) {/* */}     /* Wait till no operation is on going */

    NVIC_SystemReset();                                       /* Reboot                             */
  }
#else
  #define FLASH_EN                      NO
#endif


__STATIC_INLINE void init(void) {

  #define PORT_A_CONFIG (                         \\
    SPI_EN   * PIN_CFG(4,  O_10MHZ)               |           /* PA4:  SPI1 CS, output, 10MHz       */\\
    SPI_EN   * PIN_CFG(5,  O_AF + O_50MHZ)        |           /* PA5:  SPI1 CLK, alternate, 50MHz   */\\
    SPI_EN   * PIN_CFG(6,  I_PULL)                |           /* PA6:  SPI1 MISO, input, pull-down  */\\
    SPI_EN   * PIN_CFG(7,  O_AF + O_50MHZ)        |           /* PA7:  SPI1 MOSI, alternate, 50MHz  */\\
    EXTI_EN  * PIN_CFG(8,  I_PULL)                |           /* PA8:  EXTI Line, input, pull-up    */\\
    USART_EN * PIN_CFG(9,  O_AF + O_10MHZ)        |           /* PA9:  USART1 TX, alternate, 10MHz  */\\
    USART_EN * PIN_CFG(10, I_PULL)                |           /* PA10: USART1 RX, input, pull-down  */\\
    SWD_EN   * PIN_CFG(13, I_PULL)                |           /* PA13: SWDIO, input, pull-up        */\\
    SWD_EN   * PIN_CFG(14, I_PULL)                |           /* PA14: SWCLK, input, pull-down      */\\
    TIM2_EN  * PIN_CFG(15, O_AF + O_10MHZ)                    /* PA15: TIM2 CH2, alternate, 10MHz   */\\
  )

  #define PORT_A_STATE (                          \\
    SPI_EN   * PULL_UP(4)                         |           /* Pull-up SPI1 CS pin                */\\
    SPI_EN   * PULL_DOWN(6)                       |           /* Pull-down SPI1 MISO pin            */\\
    EXTI_EN  * PULL_UP(8)                         |           /* Pull-up EXTI pin                   */\\
    USART_EN * PULL_DOWN(10)                      |           /* Pull-down USART1 RX pin            */\\
    SWD_EN   * PULL_UP(13)                        |           /* Pull-up SWDIO pin                  */\\
    SWD_EN   * PULL_DOWN(14)                                  /* Pull-down SWCLK pin                */\\
  )

  #define IOPA_EN (PORT_A_CONFIG != 0)

  #define PORT_B_CONFIG (                         \\
    BTN_EN   * PIN_CFG(0,  I_PULL)                |           /* PB0:  BUTTON 1, input, pull-up     */\\
    BTN_EN   * PIN_CFG(1,  I_PULL)                |           /* PB1:  BUTTON 2, input, pull-up     */\\
    I2C_EN   * PIN_CFG(6,  O_AF + O_OD + O_10MHZ) |           /* PB6:  I2C1 SCL, altern, open drain */\\
    I2C_EN   * PIN_CFG(7,  O_AF + O_OD + O_10MHZ)             /* PB7:  I2C1 SDA, altern, open drain */\\
  )

  #define PORT_B_STATE (                          \\
    BTN_EN   * PULL_UP(0)                         |           /* Pull-up PB0 pin (BUTTON 1)         */\\
    BTN_EN   * PULL_UP(1)                                     /* Pull-up PB1 pin (BUTTON 2)         */\\
  )

  #define IOPB_EN (PORT_B_CONFIG != 0)

  #define PORT_C_CONFIG PIN_CFG(13, O_2MHZ)                   /* PC13: output, push-pull, 2Mhz      */
  #define PORT_C_STATE PIN_HIGH(13)                           /* Set PC13 pin HIGH (LED off)        */
  #define IOPC_EN (PORT_C_CONFIG != 0)

  #define GATE_CLOCK(BUS, PER)      RCC_ ## BUS ## ENR_ ## PER ## EN

  #define AHB_CONFIG (                            \\
    DMA_EN   * GATE_CLOCK(AHB, DMA1)              |           /* Enable clock for DMA1              */\\
    0        * GATE_CLOCK(AHB, SRAM)              |           /* Enable clock for SRAM while Sleep  */\\
    0        * GATE_CLOCK(AHB, FLITF)             |           /* Enable clock for FLITF while Sleep */\\
    CRC_EN   * GATE_CLOCK(AHB, CRC)               |           /* Enable clock for CRC               */\\
    RNG_EN   * GATE_CLOCK(AHB, CRC)                           /* Enable clock for CRC               */\\
  )

  #define APB1_CONFIG (                           \\
    0        * GATE_CLOCK(APB1, TIM3)             |           /* Enable clock for Timer 3           */\\
    0        * GATE_CLOCK(APB1, TIM4)             |           /* Enable clock for Timer 4           */\\
    0        * GATE_CLOCK(APB1, CAN1)             |           /* Enable clock for CAN 1             */\\
    0        * GATE_CLOCK(APB1, SPI2)             |           /* Enable clock for SPI 2             */\\
    0        * GATE_CLOCK(APB1, USART2)           |           /* Enable clock for USART 2           */\\
    0        * GATE_CLOCK(APB1, USART3)           |           /* Enable clock for USART 3           */\\
    0        * GATE_CLOCK(APB1, I2C2)             |           /* Enable clock for I2C 2             */\\
    WWDG_EN  * GATE_CLOCK(APB1, WWDG)             |           /* Enable clock for Window Watchdog   */\\
    TIM2_EN  * GATE_CLOCK(APB1, TIM2)             |           /* Enable clock for Timer 2           */\\
    I2C_EN   * GATE_CLOCK(APB1, I2C1)             |           /* Enable clock for I2C 1             */\\
    RTC_EN   * GATE_CLOCK(APB1, BKP)              |           /* Enable clock for Backup interface  */\\
    RTC_EN   * GATE_CLOCK(APB1, PWR)                          /* Enable clock for Power interface   */\\
  )

  #define APB2_CONFIG (                           \\
    0        * GATE_CLOCK(APB2, TIM1)             |           /* Enable clock for Timer 1           */\\
    0        * GATE_CLOCK(APB2, ADC2)             |           /* Enable clock for ADC 1             */\\
    USART_EN * GATE_CLOCK(APB2, USART1)           |           /* Enable clock for USART 1           */\\
    SPI_EN   * GATE_CLOCK(APB2, SPI1)             |           /* Enable clock for SPI 1             */\\
    ADC_EN   * GATE_CLOCK(APB2, ADC1)             |           /* Enable clock for ADC 1             */\\
    IOPA_EN  * GATE_CLOCK(APB2, IOPA)             |           /* Enable clock for I/O port A        */\\
    IOPB_EN  * GATE_CLOCK(APB2, IOPB)             |           /* Enable clock for I/O port B        */\\
    IOPC_EN  * GATE_CLOCK(APB2, IOPC)             |           /* Enable clock for I/O port C        */\\
               GATE_CLOCK(APB2, AFIO)                         /* Enable clock for Alt. Function I/O */\\
  )

  #if AHB_CONFIG
    RCC->AHBENR = AHB_CONFIG;                                 /* Gate AHB clock if required         */
  #endif

  #if APB1_CONFIG
    RCC->APB1ENR = APB1_CONFIG;                               /* Gate APB1 clock if required        */
  #endif

  #if APB2_CONFIG
    RCC->APB2ENR = APB2_CONFIG;                               /* Gate APB2 clock if required        */
  #endif

  #if PORT_A_CONFIG
    *(__IO uint64_t*) GPIOA_BASE = PORT_A_CONFIG;             /* Init GPIOA if CONFIG is not empty  */
    #if PORT_A_STATE
      GPIOA->BSRR = PORT_A_STATE;                             /* Set GPIOA pins state if required   */
    #endif
  #endif

  #if PORT_B_CONFIG
    *(__IO uint64_t*) GPIOB_BASE = PORT_B_CONFIG;             /* Init GPIOB if CONFIG is not empty  */
    #if PORT_B_STATE
      GPIOB->BSRR = PORT_B_STATE;                             /* Set GPIOB pins state if required   */
    #endif
  #endif

  #if PORT_C_CONFIG
    *(__IO uint64_t*) GPIOC_BASE = PORT_C_CONFIG;             /* Init GPIOC if CONFIG is not empty  */
    #if PORT_C_STATE
      GPIOC->BSRR = PORT_C_STATE;                             /* Set GPIOC pins state if required   */
    #endif
  #endif

  AFIO->MAPR = (
    #if SWD_EN
      AFIO_MAPR_SWJ_CFG_JTAGDISABLE          |                /* Disable JTAG, enable SWD           */
    #else
      AFIO_MAPR_SWJ_CFG_DISABLE              |                /* Disable both JTAG and SWD          */
    #endif
    TIM2_EN * AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1       /* Remap CH1/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */
  );

  #if HSE_EN
    SET_REG_BIT(RCC->CR, RCC_CR_HSEON);                       /* Switch HSE on                      */
    while(!READ_REG_BIT(RCC->CR, RCC_CR_HSERDY)) {/* */}      /* Wait until HSE becomes ready       */

    #if defined OVRCLK && OVRCLK != 0
      #define _RCC_CFGR (                                     /* 112 MHz:                           */\\
                RCC_CFGR_PLLSRC                  |            /*   PLL Source is HSE                */\\
                RCC_CFGR_PLLMULL14               |            /*   PLL multiplier is 14             */\\
                RCC_CFGR_ADCPRE_DIV8                          /*   ADC clock divider is 8           */\\
              )
      #define HCLK     112000000UL
    #else
      #define _RCC_CFGR (                                     /* 72 MHz:                            */\\
                RCC_CFGR_PLLSRC                  |            /*   PLL Source is HSE                */\\
                RCC_CFGR_PLLMULL9                |            /*   PLL multiplier is 9              */\\
                RCC_CFGR_ADCPRE_DIV6                          /*   ADC clock divider is 6           */\\
              )
      #define HCLK     72000000UL
    #endif

    #define _RCC_CR   RCC_CR_PLLON | RCC_CR_HSEON
  #else
    #define _RCC_CFGR RCC_CFGR_PLLMULL16                      /* 64 MHz: PLLSrc = HSI / 2, Mul = 16 */
    #define _RCC_CR   RCC_CR_PLLON
    #define HCLK     64000000UL
  #endif

  #if PLL_EN

    RCC->CFGR = _RCC_CFGR;                                    /* Configure PLL                      */
    RCC->CR = _RCC_CR;                                        /* Switch PLL on                      */
    while(!READ_REG_BIT(RCC->CR, RCC_CR_PLLRDY)) { /* */}     /* Wait until PLL becomes ready       */
    FLASH->ACR = FLASH_ACR_LATENCY_1;                         /* Set flash latency to 2             */
    RCC->CFGR = (
      _RCC_CFGR            |
      RCC_CFGR_SW_PLL      |                                  /* Set PLL as system clock source     */
      RCC_CFGR_PPRE1_DIV2                                     /* Set APB1 clock as HCLK / 2         */
    );

    #define APB1_CLK ((HCLK) / 2)

  #else

    #undef  HCLK
    #define HCLK     8000000UL
    #define APB1_CLK HCLK

  #endif

  #if RNG_EN
    #if !RTC_EN && !ADC_EN
      SysTick->LOAD = HCLK / 40000 - 1;                       /* Set SysTick reload register        */
      SysTick->CTRL = SysTick_CTRL_ENABLE_Msk    |            /* Start SysTick timer (HCLK / 8)     */
                      SysTick_CTRL_CLKSOURCE_Msk |
                      SysTick_CTRL_TICKINT_Msk;               /* Enable SysTick exception request   */

      for(int i = 0; i < 10000; i++) {
        SET_REG_BIT(RCC->CSR, RCC_CSR_LSION);                 /* Enable LSI oscillator              */
        while(!READ_REG_BIT(RCC->CSR, RCC_CSR_LSIRDY)) { }    /* wait till oscillator switches on   */
        CRC->DR = SysTick->VAL;                               /* process counter                    */

        CLEAR_REG_BIT(RCC->CSR, RCC_CSR_LSION);               /* Disable LSI oscillator             */
        while(READ_REG_BIT(RCC->CSR, RCC_CSR_LSIRDY)) { }     /* wait till oscillator switches off  */
        CRC->DR = SysTick->VAL;                               /* process counter                    */
      }
    #else
      prnd();
    #endif
    srnd(CRC->DR);
  #endif

  SysTick->LOAD = HCLK / 8000 - 1;                            /* Set SysTick reload register        */

  SysTick->CTRL = SysTick_CTRL_ENABLE_Msk |                   /* Start SysTick timer (HCLK / 8)     */
                  SysTick_CTRL_TICKINT_Msk;                   /* Enable SysTick exception request   */

  #if USART_EN
    #if DMA_EN
      USART1->CR3 = USART_CR3_DMAT;                           /* (1 << 7) DMA Enable Transmitter    */
    #endif
    USART1->BRR = (HCLK + BAUDRATE / 2) / BAUDRATE;           /* Configure USART baud rate          */
    USART1->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE; /* Enable USART peripheral            */
  #endif

  #if ADC_EN
    ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_TSVREFE | ADC_CR2_CONT;/* ADC enable, VrefInt enable, count  */

    DELAY_MS(2);                                              /* Before starting a calibration,
                                                                 the ADC must have been in power-on
                                                                 state for at least two ADC clock
                                                                 cycles.                            */

    SET_REG_BIT(ADC1->CR2, ADC_CR2_CAL);                      /* Start ADC1 calibration             */

    while (READ_REG_BIT(ADC1->CR2, ADC_CR2_CAL)) {   /* Wait until ADC calibration completes */   }

                                                                                                    /*
      The Temperature sensor is connected to channel ADCx_IN16 and the internal reference voltage
      VREFINT is connected to ADCx_IN17. These two internal channels can be selected and converted
      as injected or regular channels.                                                              */

    ADC1->SMPR1 = _ADC_SMPR1(16, 239) | _ADC_SMPR1(17, 239);
    ADC1->SQR3  = _ADC_SQR3(1, 16);
    ADC1->SQR1  = _ADC_SQR1_LEN(1);
                                                                                                    /*
      If any other bit in this register apart from ADON is changed at the same time,
      then conversion is not triggered. This is to prevent triggering an erroneous conversion.      */

    SET_REG_BIT(ADC1->CR2, ADC_CR2_ADON);                     /* Start continuous conversion        */

    #if RNG_EN
      {
        unsigned rbits = 0;
        for(unsigned i = 0; i < 32; i++) {
          rbits = (rbits << 1) | adc_get_random_bit();
        }
        srnd(rbits);
      }
    #endif

    #if 0
      /* ADC1 interrupt Init */
      NVIC_SetPriority(ADC1_2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
      NVIC_ClearPendingIRQ(ADC1_2_IRQn);
      NVIC_EnableIRQ(ADC1_2_IRQn);
    #endif
  #endif

  #if I2C_EN
    I2C1->CCR = _I2C_CCR;                                     /* Write CCR when I2C is disabled     */
    I2C1->TRISE = _I2C_TRISE;                                 /* Maximum rise time in Fm/Sm mode    */
    I2C1->CR2 = APB1_CLK / 1000000;                           /* Configure Peripheral Clock Freq.   */
    I2C1->CR1 = I2C_CR1_PE;                                   /* Enable I2C1 Peripheral             */
  #endif

  #if SPI_EN
    SPI1->CR1 = (

      #if defined USE_PLL && USE_PLL != 0
        SPI_CR1_BR_0       |                                  /* Configure baudrate as HCLK / 4     */
      #endif

      SPI_CR1_MSTR         |                                  /* Select Master mode                 */
      SPI_CR1_SSM          |                                  /* Enable Software Slave Management   */
      SPI_CR1_SSI          |                                  /* Set Internal slave select bit      */
      SPI_CR1_SPE                                             /* Enable SPI1 Peripheral             */
    );
  #endif

  #if DMA_EN
    #define DMA1_Channel2_CCR (\\
      1 * DMA_CCR_EN      |  /* (1 << 0)           Channel enable                       0x00000001  */\\
      0 * DMA_CCR_TCIE    |  /* (1 << 1)           Transfer complete interrupt enable   0x00000002  */\\
      0 * DMA_CCR_HTIE    |  /* (1 << 2)           Half Transfer interrupt enable       0x00000004  */\\
      0 * DMA_CCR_TEIE    |  /* (1 << 3)           Transfer error interrupt enable      0x00000008  */\\
      1 * DMA_CCR_DIR     |  /* (1 << 4)           Data transfer direction              0x00000010  */\\
      1 * DMA_CCR_CIRC    |  /* (1 << 5)           Circular mode                        0x00000020  */\\
      0 * DMA_CCR_PINC    |  /* (1 << 6)           Peripheral increment mode            0x00000040  */\\
      1 * DMA_CCR_MINC    |  /* (1 << 7)           Memory increment mode                0x00000080  */\\
      0 * DMA_CCR_PSIZE   |  /* (3 << 8)           PSIZE[1:0] bits (Peripheral size)    0x00000300  */\\
      0 * DMA_CCR_PSIZE_0 |  /* (1 << 8)             0x00000100                                     */\\
      1 * DMA_CCR_PSIZE_1 |  /* (2 << 8)             0x00000200                                     */\\
      0 * DMA_CCR_MSIZE   |  /* (3 << 10)          MSIZE[1:0] bits (Memory size)        0x00000C00  */\\
      0 * DMA_CCR_MSIZE_0 |  /* (1 << 10)            0x00000400                                     */\\
      1 * DMA_CCR_MSIZE_1 |  /* (2 << 10)            0x00000800                                     */\\
      0 * DMA_CCR_PL      |  /* (3 << 12)          PL[1:0] bits(Channel Priority level) 0x00003000  */\\
      0 * DMA_CCR_PL_0    |  /* (1 << 12)            0x00001000                                     */\\
      0 * DMA_CCR_PL_1    |  /* (2 << 12)            0x00002000                                     */\\
      0 * DMA_CCR_MEM2MEM    /* (1 << 14)          Memory to memory mode                0x00004000  */\\
    )

    {
      extern const unsigned blink_pattern[30];

      DMA1_Channel2->CMAR  = (unsigned)&blink_pattern;                               /* 0x40020028  */
      DMA1_Channel2->CNDTR = sizeof(blink_pattern) / sizeof(blink_pattern[0]);       /* 0x40020020  */
      DMA1_Channel2->CPAR  = (unsigned)&GPIOC->BSRR;                                 /* 0x40020024  */
      DMA1_Channel2->CCR   = DMA1_Channel2_CCR;                                      /* 0x4002001C  */
    }

    #define DMA1_Channel4_CCR (\\
      1 * DMA_CCR_EN      |  /* (1 << 0)           Channel enable                       0x00000001  */\\
      0 * DMA_CCR_TCIE    |  /* (1 << 1)           Transfer complete interrupt enable   0x00000002  */\\
      0 * DMA_CCR_HTIE    |  /* (1 << 2)           Half Transfer interrupt enable       0x00000004  */\\
      0 * DMA_CCR_TEIE    |  /* (1 << 3)           Transfer error interrupt enable      0x00000008  */\\
      1 * DMA_CCR_DIR     |  /* (1 << 4)           Data transfer direction              0x00000010  */\\
      0 * DMA_CCR_CIRC    |  /* (1 << 5)           Circular mode                        0x00000020  */\\
      0 * DMA_CCR_PINC    |  /* (1 << 6)           Peripheral increment mode            0x00000040  */\\
      1 * DMA_CCR_MINC    |  /* (1 << 7)           Memory increment mode                0x00000080  */\\
      0 * DMA_CCR_PSIZE   |  /* (3 << 8)           PSIZE[1:0] bits (Peripheral size)    0x00000300  */\\
      0 * DMA_CCR_PSIZE_0 |  /* (1 << 8)             0x00000100                                     */\\
      0 * DMA_CCR_PSIZE_1 |  /* (2 << 8)             0x00000200                                     */\\
      0 * DMA_CCR_MSIZE   |  /* (3 << 10)          MSIZE[1:0] bits (Memory size)        0x00000C00  */\\
      0 * DMA_CCR_MSIZE_0 |  /* (1 << 10)            0x00000400                                     */\\
      0 * DMA_CCR_MSIZE_1 |  /* (2 << 10)            0x00000800                                     */\\
      0 * DMA_CCR_PL      |  /* (3 << 12)          PL[1:0] bits(Channel Priority level) 0x00003000  */\\
      0 * DMA_CCR_PL_0    |  /* (1 << 12)            0x00001000                                     */\\
      0 * DMA_CCR_PL_1    |  /* (2 << 12)            0x00002000                                     */\\
      0 * DMA_CCR_MEM2MEM    /* (1 << 14)          Memory to memory mode                0x00004000  */\\
    )

    DMA1_Channel4->CPAR  = (unsigned)&USART1->DR;                                    /* 0x4002004C  */

  #endif


  #if TIM2_EN

    #define DM DMA_EN

    #define TIM2_PSC (HCLK / 10000 - 1)  /* 0..0xFFFF - Prescaler Value                             */
    #define TIM2_ARR (300 - 1)           /* 0..0xFFFF - actual auto-reload Value                    */
    #define TIM2_CCR1 (TIM2_ARR / 2 - 1) /* 0..0xFFFF - Capture/Compare 1 Value                     */

    #define TIM2_EGR (    \\
      1 * TIM_EGR_UG      |  /* (1 << 0)    Update Generation                           0x00000001  */\\
      0 * TIM_EGR_CC1G    |  /* (1 << 1)    Capture/Compare 1 Generation                0x00000002  */\\
      0 * TIM_EGR_CC2G    |  /* (1 << 2)    Capture/Compare 2 Generation                0x00000004  */\\
      0 * TIM_EGR_CC3G    |  /* (1 << 3)    Capture/Compare 3 Generation                0x00000008  */\\
      0 * TIM_EGR_CC4G    |  /* (1 << 4)    Capture/Compare 4 Generation                0x00000010  */\\
      0 * TIM_EGR_COMG    |  /* (1 << 5)    Capture/Compare Control Update Generation   0x00000020  */\\
      0 * TIM_EGR_TG      |  /* (1 << 6)    Trigger Generation                          0x00000040  */\\
      0 * TIM_EGR_BG         /* (1 << 7)    Break Generation                            0x00000080  */\\
    )

    #define TIM2_DIER (   \\
      1 * TIM_DIER_UIE    |  /* (1 << 0)    Update interrupt enable                     0x00000001  */\\
                                                                                                      \\
      0 * TIM_DIER_CC1IE  |  /* (1 << 1)    Capture/Compare 1 interrupt enable          0x00000002  */\\
      0 * TIM_DIER_CC2IE  |  /* (1 << 2)    Capture/Compare 2 interrupt enable          0x00000004  */\\
      0 * TIM_DIER_CC3IE  |  /* (1 << 3)    Capture/Compare 3 interrupt enable          0x00000008  */\\
      0 * TIM_DIER_CC4IE  |  /* (1 << 4)    Capture/Compare 4 interrupt enable          0x00000010  */\\
                                                                                                      \\
      0 * TIM_DIER_TIE    |  /* (1 << 6)    Trigger interrupt enable                    0x00000040  */\\
                                                                                                      \\
      DM * TIM_DIER_UDE   |  /* (1 << 8)    Update DMA request enable                   0x00000100  */\\
                                                                                                      \\
      0 * TIM_DIER_CC1DE  |  /* (1 << 9)    Capture/Compare 1 DMA request enable        0x00000200  */\\
      0 * TIM_DIER_CC2DE  |  /* (1 << 10)   Capture/Compare 2 DMA request enable        0x00000400  */\\
      0 * TIM_DIER_CC3DE  |  /* (1 << 11)   Capture/Compare 3 DMA request enable        0x00000800  */\\
      0 * TIM_DIER_CC4DE  |  /* (1 << 12)   Capture/Compare 4 DMA request enable        0x00001000  */\\
                                                                                                      \\
      0 * TIM_DIER_TDE       /* (1 << 14)   Trigger DMA request enable                  0x00004000  */\\
    )

    #define TIM2_CCMR1 (     \\
      0 * TIM_CCMR1_CC1S     |  /* (3 << 0)    CC1S[1:0] bits (Capture/Compare 1 Sel.)  0x00000003  */\\
      0 * TIM_CCMR1_CC1S_0   |  /* (1 << 0)      0x00000001                                         */\\
      0 * TIM_CCMR1_CC1S_1   |  /* (2 << 0)      0x00000002                                         */\\
      0 * TIM_CCMR1_OC1FE    |  /* (1 << 2)    Output Compare 1 Fast enable             0x00000004  */\\
      0 * TIM_CCMR1_OC1PE    |  /* (1 << 3)    Output Compare 1 Preload enable          0x00000008  */\\
      0 * TIM_CCMR1_OC1M     |  /* (7 << 4)    OC1M[2:0] bits (Output Compare 1 Mode)   0x00000070  */\\
      0 * TIM_CCMR1_OC1M_0   |  /* (1 << 4)      0x00000010                                         */\\
      1 * TIM_CCMR1_OC1M_1   |  /* (2 << 4)      0x00000020                                         */\\
      1 * TIM_CCMR1_OC1M_2   |  /* (4 << 4)      0x00000040                                         */\\
      0 * TIM_CCMR1_OC1CE    |  /* (1 << 7)    Output Compare 1 Clear Enable            0x00000080  */\\
      0 * TIM_CCMR1_CC2S     |  /* (3 << 8)    CC2S[1:0] bits (Capture/Compare 2 Sel.)  0x00000300  */\\
      0 * TIM_CCMR1_CC2S_0   |  /* (1 << 8)      0x00000100                                         */\\
      0 * TIM_CCMR1_CC2S_1   |  /* (2 << 8)      0x00000200                                         */\\
      0 * TIM_CCMR1_OC2FE    |  /* (1 << 10)   Output Compare 2 Fast enable             0x00000400  */\\
      0 * TIM_CCMR1_OC2PE    |  /* (1 << 11)   Output Compare 2 Preload enable          0x00000800  */\\
      0 * TIM_CCMR1_OC2M     |  /* (7 << 12)   OC2M[2:0] bits (Output Compare 2 Mode)   0x00007000  */\\
      0 * TIM_CCMR1_OC2M_0   |  /* (1 << 12)     0x00001000                                         */\\
      0 * TIM_CCMR1_OC2M_1   |  /* (2 << 12)     0x00002000                                         */\\
      0 * TIM_CCMR1_OC2M_2   |  /* (4 << 12)     0x00004000                                         */\\
      0 * TIM_CCMR1_OC2CE    |  /* (1 << 15)   Output Compare 2 Clear Enable            0x00008000  */\\
      0 * TIM_CCMR1_IC1PSC   |  /* (3 << 2)    IC1PSC[1:0] bits (Input Capture 1 Psc.)  0x0000000C  */\\
      0 * TIM_CCMR1_IC1PSC_0 |  /* (1 << 2)      0x00000004                                         */\\
      0 * TIM_CCMR1_IC1PSC_1 |  /* (2 << 2)      0x00000008                                         */\\
      0 * TIM_CCMR1_IC1F     |  /* (0xF << 4)  IC1F[3:0] bits (Input Capture 1 Filter)  0x000000F0  */\\
      0 * TIM_CCMR1_IC1F_0   |  /* (1 << 4)      0x00000010                                         */\\
      0 * TIM_CCMR1_IC1F_1   |  /* (2 << 4)      0x00000020                                         */\\
      0 * TIM_CCMR1_IC1F_2   |  /* (4 << 4)      0x00000040                                         */\\
      0 * TIM_CCMR1_IC1F_3   |  /* (8 << 4)      0x00000080                                         */\\
      0 * TIM_CCMR1_IC2PSC   |  /* (3 << 10)   IC2PSC[1:0] bits (Input Capture 2 Psc.)  0x00000C00  */\\
      0 * TIM_CCMR1_IC2PSC_0 |  /* (1 << 10)     0x00000400                                         */\\
      0 * TIM_CCMR1_IC2PSC_1 |  /* (2 << 10)     0x00000800                                         */\\
      0 * TIM_CCMR1_IC2F     |  /* (0xF << 12) IC2F[3:0] bits (Input Capture 2 Filter)  0x0000F000  */\\
      0 * TIM_CCMR1_IC2F_0   |  /* (1 << 12)     0x00001000                                         */\\
      0 * TIM_CCMR1_IC2F_1   |  /* (2 << 12)     0x00002000                                         */\\
      0 * TIM_CCMR1_IC2F_2   |  /* (4 << 12)     0x00004000                                         */\\
      0 * TIM_CCMR1_IC2F_3      /* (8 << 12)     0x00008000                                         */\\
    )

    #define TIM2_CCER (      \\
      1 * TIM_CCER_CC1E      |  /* (1 << 0)   Capture/Compare 1 output enable           0x00000001  */\\
      0 * TIM_CCER_CC1P      |  /* (1 << 1)   Capture/Compare 1 output Polarity         0x00000002  */\\
                                                                                                      \\
      0 * TIM_CCER_CC2E      |  /* (1 << 4)   Capture/Compare 2 output enable           0x00000010  */\\
      0 * TIM_CCER_CC2P      |  /* (1 << 5)   Capture/Compare 2 output Polarity         0x00000020  */\\
                                                                                                      \\
      0 * TIM_CCER_CC3E      |  /* (1 << 8)   Capture/Compare 3 output enable           0x00000100  */\\
      0 * TIM_CCER_CC3P      |  /* (1 << 9)   Capture/Compare 3 output Polarity         0x00000200  */\\
                                                                                                      \\
      0 * TIM_CCER_CC4E      |  /* (1 << 12)  Capture/Compare 4 output enable           0x00001000  */\\
      0 * TIM_CCER_CC4P         /* (1 << 13)  Capture/Compare 4 output Polarity         0x00002000  */\\
    )

    NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
    NVIC_ClearPendingIRQ(TIM2_IRQn);
    NVIC_EnableIRQ(TIM2_IRQn);                                /* Enable TIM2 Interrupt              */

    #define TIM2_CR1 (  \\
      1 * TIM_CR1_CEN   |  /* (1 << 0)  Counter enable                                  0x00000001  */\\
      0 * TIM_CR1_UDIS  |  /* (1 << 1)  Update disable                                  0x00000002  */\\
      0 * TIM_CR1_URS   |  /* (1 << 2)  Update request source                           0x00000004  */\\
      0 * TIM_CR1_OPM   |  /* (1 << 3)  One pulse mode                                  0x00000008  */\\
      0 * TIM_CR1_DIR   |  /* (1 << 4)  Direction                                       0x00000010  */\\
      0 * TIM_CR1_CMS   |  /* (3 << 5)  CMS[1:0] bits (Center-aligned mode selection)   0x00000060  */\\
      0 * TIM_CR1_CMS_0 |  /* (1 << 5)    0x00000020                                                */\\
      0 * TIM_CR1_CMS_1 |  /* (2 << 5)    0x00000040                                                */\\
      0 * TIM_CR1_ARPE  |  /* (1 << 7)  Auto-reload preload enable                      0x00000080  */\\
      0 * TIM_CR1_CKD   |  /* (3 << 8)  CKD[1:0] bits (clock division)                  0x00000300  */\\
      0 * TIM_CR1_CKD_0 |  /* (1 << 8)    0x00000100                                                */\\
      0 * TIM_CR1_CKD_1    /* (2 << 8)    0x00000200                                                */\\
    )

    #if TIM2_ARR != 0
      TIM2->ARR = TIM2_ARR;  /* 0x4000002C: TIM2 auto-reload register                               */
    #endif

    #if TIM2_CCR1 != 0
      TIM2->CCR1 = TIM2_CCR1;/* 0x40000034: TIM2 capture/compare register 1                         */
    #endif

    #if TIM2_PSC != 0
      TIM2->PSC = TIM2_PSC;  /* 0x40000028: TIM2 prescaler register                                 */
      #if TIM2_EGR != 0
        TIM2->EGR = TIM2_EGR;/* 0x40000014: TIM2 event generation register                          */
        TIM2->SR = 0;        /* Reset TIM2 status flags                                             */
      #endif
    #endif

    #if TIM2_DIER != 0
      TIM2->DIER = TIM2_DIER;/* 0x4000000C: TIM DMA/interrupt enable register                       */
    #endif

    #if TIM2_CCMR1 != 0
      TIM2->CCMR1 = TIM2_CCMR1; /* 0x40000018: TIM2 capt/comp mode register 1                       */
    #endif

    #if TIM2_CCER != 0
      TIM2->CCER = TIM2_CCER;   /* 0x40000020: TIM capture/compare enable register                  */
    #endif

    #if TIM2_CR1 != 0
      TIM2->CR1 = TIM2_CR1;/* 0x40000000: TIM control register 1                                    */
    #endif

  #endif

  #if IWDG_EN

    SET_REG_BIT(RCC->CSR, RCC_CSR_LSION);                     /* Enable LSI oscillator              */
    while(!READ_REG_BIT(RCC->CSR, RCC_CSR_LSIRDY)) {
      /* wait until LSI oscillations become stable */
    }

    IWDG->KR = 0x5555;
                                                                                                    /*
      Min/max IWDG timeout period (in ms) at 40 kHz (LSI)(1)
    =======================================================================
      Prescaler      PR[2:0] bits       Min timeout         Max timeout
       divider                        RL[11:0]= 0x000     RL[11:0]= 0xFFF

          /4              0                 0.1                409.6
          /8              1                 0.2                819.2
         /16              2                 0.4               1638.4
         /32              3                 0.8               3276.8
         /64              4                 1.6               6553.6
        /128              5                 3.2              13107.2
        /256              6 (or 7)          6.4              26214.4
    =======================================================================                         */

    IWDG->PR = 2;
    IWDG->RLR = 0xFFF;

    IWDG->KR = 0xCCCC;                                        /*  Start the watchdog                */
  #endif /* IWDG_EN */

  #if EXTI_EN

    #define INIT_AFIO_EXTICR_0   (     \\
      0 * AFIO_EXTICR1_EXTI0           | /*  0x0000000F EXTI 0 configuration                        */\\
      0 * AFIO_EXTICR1_EXTI1           | /*  0x000000F0 EXTI 1 configuration                        */\\
      0 * AFIO_EXTICR1_EXTI2           | /*  0x00000F00 EXTI 2 configuration                        */\\
      0 * AFIO_EXTICR1_EXTI3           | /*  0x0000F000 EXTI 3 configuration                        */\\
                                                                                                      \\
      0 * AFIO_EXTICR1_EXTI0_PA        | /*  0x00000000 PA[0] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI0_PB        | /*  0x00000001 PB[0] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI0_PC        | /*  0x00000002 PC[0] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI0_PD        | /*  0x00000003 PD[0] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI0_PE        | /*  0x00000004 PE[0] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI0_PF        | /*  0x00000005 PF[0] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI0_PG        | /*  0x00000006 PG[0] pin                                   */\\
                                                                                                      \\
      0 * AFIO_EXTICR1_EXTI1_PA        | /*  0x00000000 PA[1] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI1_PB        | /*  0x00000010 PB[1] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI1_PC        | /*  0x00000020 PC[1] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI1_PD        | /*  0x00000030 PD[1] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI1_PE        | /*  0x00000040 PE[1] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI1_PF        | /*  0x00000050 PF[1] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI1_PG        | /*  0x00000060 PG[1] pin                                   */\\
                                                                                                      \\
      0 * AFIO_EXTICR1_EXTI2_PA        | /*  0x00000000 PA[2] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI2_PB        | /*  0x00000100 PB[2] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI2_PC        | /*  0x00000200 PC[2] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI2_PD        | /*  0x00000300 PD[2] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI2_PE        | /*  0x00000400 PE[2] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI2_PF        | /*  0x00000500 PF[2] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI2_PG        | /*  0x00000600 PG[2] pin                                   */\\
                                                                                                      \\
      0 * AFIO_EXTICR1_EXTI3_PA        | /*  0x00000000 PA[3] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI3_PB        | /*  0x00001000 PB[3] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI3_PC        | /*  0x00002000 PC[3] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI3_PD        | /*  0x00003000 PD[3] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI3_PE        | /*  0x00004000 PE[3] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI3_PF        | /*  0x00005000 PF[3] pin                                   */\\
      0 * AFIO_EXTICR1_EXTI3_PG          /*  0x00006000 PG[3] pin                                   */\\
    )

    #define INIT_AFIO_EXTICR_1   (     \\
      0 * AFIO_EXTICR2_EXTI4           | /*  0x0000000F EXTI 4 configuration                        */\\
      0 * AFIO_EXTICR2_EXTI5           | /*  0x000000F0 EXTI 5 configuration                        */\\
      0 * AFIO_EXTICR2_EXTI6           | /*  0x00000F00 EXTI 6 configuration                        */\\
      0 * AFIO_EXTICR2_EXTI7           | /*  0x0000F000 EXTI 7 configuration                        */\\
                                                                                                      \\
      0 * AFIO_EXTICR2_EXTI4_PA        | /*  0x00000000 PA[4] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI4_PB        | /*  0x00000001 PB[4] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI4_PC        | /*  0x00000002 PC[4] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI4_PD        | /*  0x00000003 PD[4] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI4_PE        | /*  0x00000004 PE[4] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI4_PF        | /*  0x00000005 PF[4] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI4_PG        | /*  0x00000006 PG[4] pin                                   */\\
                                                                                                      \\
      0 * AFIO_EXTICR2_EXTI5_PA        | /*  0x00000000 PA[5] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI5_PB        | /*  0x00000010 PB[5] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI5_PC        | /*  0x00000020 PC[5] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI5_PD        | /*  0x00000030 PD[5] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI5_PE        | /*  0x00000040 PE[5] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI5_PF        | /*  0x00000050 PF[5] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI5_PG        | /*  0x00000060 PG[5] pin                                   */\\
                                                                                                      \\
      0 * AFIO_EXTICR2_EXTI6_PA        | /*  0x00000000 PA[6] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI6_PB        | /*  0x00000100 PB[6] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI6_PC        | /*  0x00000200 PC[6] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI6_PD        | /*  0x00000300 PD[6] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI6_PE        | /*  0x00000400 PE[6] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI6_PF        | /*  0x00000500 PF[6] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI6_PG        | /*  0x00000600 PG[6] pin                                   */\\
                                                                                                      \\
      0 * AFIO_EXTICR2_EXTI7_PA        | /*  0x00000000 PA[7] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI7_PB        | /*  0x00001000 PB[7] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI7_PC        | /*  0x00002000 PC[7] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI7_PD        | /*  0x00003000 PD[7] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI7_PE        | /*  0x00004000 PE[7] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI7_PF        | /*  0x00005000 PF[7] pin                                   */\\
      0 * AFIO_EXTICR2_EXTI7_PG          /*  0x00006000 PG[7] pin                                   */\\
    )

    #define INIT_AFIO_EXTICR_2   (     \\
      0 * AFIO_EXTICR3_EXTI8           | /*  0x0000000F EXTI 8 configuration                        */\\
      0 * AFIO_EXTICR3_EXTI9           | /*  0x000000F0 EXTI 9 configuration                        */\\
      0 * AFIO_EXTICR3_EXTI10          | /*  0x00000F00 EXTI 10 configuration                       */\\
      0 * AFIO_EXTICR3_EXTI11          | /*  0x0000F000 EXTI 11 configuration                       */\\
                                                                                                      \\
      1 * AFIO_EXTICR3_EXTI8_PA        | /*  0x00000000 PA[8] pin                                   */\\
      0 * AFIO_EXTICR3_EXTI8_PB        | /*  0x00000001 PB[8] pin                                   */\\
      0 * AFIO_EXTICR3_EXTI8_PC        | /*  0x00000002 PC[8] pin                                   */\\
      0 * AFIO_EXTICR3_EXTI8_PD        | /*  0x00000003 PD[8] pin                                   */\\
      0 * AFIO_EXTICR3_EXTI8_PE        | /*  0x00000004 PE[8] pin                                   */\\
      0 * AFIO_EXTICR3_EXTI8_PF        | /*  0x00000005 PF[8] pin                                   */\\
      0 * AFIO_EXTICR3_EXTI8_PG        | /*  0x00000006 PG[8] pin                                   */\\
                                                                                                      \\
      0 * AFIO_EXTICR3_EXTI9_PA        | /*  0x00000000 PA[9] pin                                   */\\
      0 * AFIO_EXTICR3_EXTI9_PB        | /*  0x00000010 PB[9] pin                                   */\\
      0 * AFIO_EXTICR3_EXTI9_PC        | /*  0x00000020 PC[9] pin                                   */\\
      0 * AFIO_EXTICR3_EXTI9_PD        | /*  0x00000030 PD[9] pin                                   */\\
      0 * AFIO_EXTICR3_EXTI9_PE        | /*  0x00000040 PE[9] pin                                   */\\
      0 * AFIO_EXTICR3_EXTI9_PF        | /*  0x00000050 PF[9] pin                                   */\\
      0 * AFIO_EXTICR3_EXTI9_PG        | /*  0x00000060 PG[9] pin                                   */\\
                                                                                                      \\
      0 * AFIO_EXTICR3_EXTI10_PA       | /*  0x00000000 PA[10] pin                                  */\\
      0 * AFIO_EXTICR3_EXTI10_PB       | /*  0x00000100 PB[10] pin                                  */\\
      0 * AFIO_EXTICR3_EXTI10_PC       | /*  0x00000200 PC[10] pin                                  */\\
      0 * AFIO_EXTICR3_EXTI10_PD       | /*  0x00000300 PD[10] pin                                  */\\
      0 * AFIO_EXTICR3_EXTI10_PE       | /*  0x00000400 PE[10] pin                                  */\\
      0 * AFIO_EXTICR3_EXTI10_PF       | /*  0x00000500 PF[10] pin                                  */\\
      0 * AFIO_EXTICR3_EXTI10_PG       | /*  0x00000600 PG[10] pin                                  */\\
                                                                                                      \\
      0 * AFIO_EXTICR3_EXTI11_PA       | /*  0x00000000 PA[11] pin                                  */\\
      0 * AFIO_EXTICR3_EXTI11_PB       | /*  0x00001000 PB[11] pin                                  */\\
      0 * AFIO_EXTICR3_EXTI11_PC       | /*  0x00002000 PC[11] pin                                  */\\
      0 * AFIO_EXTICR3_EXTI11_PD       | /*  0x00003000 PD[11] pin                                  */\\
      0 * AFIO_EXTICR3_EXTI11_PE       | /*  0x00004000 PE[11] pin                                  */\\
      0 * AFIO_EXTICR3_EXTI11_PF       | /*  0x00005000 PF[11] pin                                  */\\
      0 * AFIO_EXTICR3_EXTI11_PG         /*  0x00006000 PG[11] pin                                  */\\
    )

    #define INIT_AFIO_EXTICR_3   (     \\
      0 * AFIO_EXTICR4_EXTI12          | /*  0x0000000F EXTI 12 configuration                       */\\
      0 * AFIO_EXTICR4_EXTI13          | /*  0x000000F0 EXTI 13 configuration                       */\\
      0 * AFIO_EXTICR4_EXTI14          | /*  0x00000F00 EXTI 14 configuration                       */\\
      0 * AFIO_EXTICR4_EXTI15          | /*  0x0000F000 EXTI 15 configuration                       */\\
                                                                                                      \\
      0 * AFIO_EXTICR4_EXTI12_PA       | /*  0x00000000 PA[12] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI12_PB       | /*  0x00000001 PB[12] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI12_PC       | /*  0x00000002 PC[12] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI12_PD       | /*  0x00000003 PD[12] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI12_PE       | /*  0x00000004 PE[12] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI12_PF       | /*  0x00000005 PF[12] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI12_PG       | /*  0x00000006 PG[12] pin                                  */\\
                                                                                                      \\
      0 * AFIO_EXTICR4_EXTI13_PA       | /*  0x00000000 PA[13] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI13_PB       | /*  0x00000010 PB[13] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI13_PC       | /*  0x00000020 PC[13] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI13_PD       | /*  0x00000030 PD[13] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI13_PE       | /*  0x00000040 PE[13] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI13_PF       | /*  0x00000050 PF[13] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI13_PG       | /*  0x00000060 PG[13] pin                                  */\\
                                                                                                      \\
      0 * AFIO_EXTICR4_EXTI14_PA       | /*  0x00000000 PA[14] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI14_PB       | /*  0x00000100 PB[14] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI14_PC       | /*  0x00000200 PC[14] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI14_PD       | /*  0x00000300 PD[14] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI14_PE       | /*  0x00000400 PE[14] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI14_PF       | /*  0x00000500 PF[14] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI14_PG       | /*  0x00000600 PG[14] pin                                  */\\
                                                                                                      \\
      0 * AFIO_EXTICR4_EXTI15_PA       | /*  0x00000000 PA[15] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI15_PB       | /*  0x00001000 PB[15] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI15_PC       | /*  0x00002000 PC[15] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI15_PD       | /*  0x00003000 PD[15] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI15_PE       | /*  0x00004000 PE[15] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI15_PF       | /*  0x00005000 PF[15] pin                                  */\\
      0 * AFIO_EXTICR4_EXTI15_PG         /*  0x00006000 PG[15] pin                                  */\\
    )

    #define INIT_EXTI_IMR        (     \\
      0 * EXTI_IMR_MR0                 | /*  0x00000001 Interrupt Mask on line 0                    */\\
      0 * EXTI_IMR_MR1                 | /*  0x00000002 Interrupt Mask on line 1                    */\\
      0 * EXTI_IMR_MR2                 | /*  0x00000004 Interrupt Mask on line 2                    */\\
      0 * EXTI_IMR_MR3                 | /*  0x00000008 Interrupt Mask on line 3                    */\\
      0 * EXTI_IMR_MR4                 | /*  0x00000010 Interrupt Mask on line 4                    */\\
      0 * EXTI_IMR_MR5                 | /*  0x00000020 Interrupt Mask on line 5                    */\\
      0 * EXTI_IMR_MR6                 | /*  0x00000040 Interrupt Mask on line 6                    */\\
      0 * EXTI_IMR_MR7                 | /*  0x00000080 Interrupt Mask on line 7                    */\\
      1 * EXTI_IMR_MR8                 | /*  0x00000100 Interrupt Mask on line 8                    */\\
      0 * EXTI_IMR_MR9                 | /*  0x00000200 Interrupt Mask on line 9                    */\\
      0 * EXTI_IMR_MR10                | /*  0x00000400 Interrupt Mask on line 10                   */\\
      0 * EXTI_IMR_MR11                | /*  0x00000800 Interrupt Mask on line 11                   */\\
      0 * EXTI_IMR_MR12                | /*  0x00001000 Interrupt Mask on line 12                   */\\
      0 * EXTI_IMR_MR13                | /*  0x00002000 Interrupt Mask on line 13                   */\\
      0 * EXTI_IMR_MR14                | /*  0x00004000 Interrupt Mask on line 14                   */\\
      0 * EXTI_IMR_MR15                | /*  0x00008000 Interrupt Mask on line 15                   */\\
      0 * EXTI_IMR_MR16                | /*  0x00010000 Interrupt Mask on line 16                   */\\
      0 * EXTI_IMR_MR17                | /*  0x00020000 Interrupt Mask on line 17                   */\\
      0 * EXTI_IMR_MR18                  /*  0x00040000 Interrupt Mask on line 18                   */\\
    )

    #define INIT_EXTI_RTSR       (     \\
      0 * EXTI_RTSR_TR0                | /*  0x00000001 Configure Rising edge trigger for line 0    */\\
      0 * EXTI_RTSR_TR1                | /*  0x00000002 Configure Rising edge trigger for line 1    */\\
      0 * EXTI_RTSR_TR2                | /*  0x00000004 Configure Rising edge trigger for line 2    */\\
      0 * EXTI_RTSR_TR3                | /*  0x00000008 Configure Rising edge trigger for line 3    */\\
      0 * EXTI_RTSR_TR4                | /*  0x00000010 Configure Rising edge trigger for line 4    */\\
      0 * EXTI_RTSR_TR5                | /*  0x00000020 Configure Rising edge trigger for line 5    */\\
      0 * EXTI_RTSR_TR6                | /*  0x00000040 Configure Rising edge trigger for line 6    */\\
      0 * EXTI_RTSR_TR7                | /*  0x00000080 Configure Rising edge trigger for line 7    */\\
      0 * EXTI_RTSR_TR8                | /*  0x00000100 Configure Rising edge trigger for line 8    */\\
      0 * EXTI_RTSR_TR9                | /*  0x00000200 Configure Rising edge trigger for line 9    */\\
      0 * EXTI_RTSR_TR10               | /*  0x00000400 Configure Rising edge trigger for line 10   */\\
      0 * EXTI_RTSR_TR11               | /*  0x00000800 Configure Rising edge trigger for line 11   */\\
      0 * EXTI_RTSR_TR12               | /*  0x00001000 Configure Rising edge trigger for line 12   */\\
      0 * EXTI_RTSR_TR13               | /*  0x00002000 Configure Rising edge trigger for line 13   */\\
      0 * EXTI_RTSR_TR14               | /*  0x00004000 Configure Rising edge trigger for line 14   */\\
      0 * EXTI_RTSR_TR15               | /*  0x00008000 Configure Rising edge trigger for line 15   */\\
      0 * EXTI_RTSR_TR16               | /*  0x00010000 Configure Rising edge trigger for line 16   */\\
      0 * EXTI_RTSR_TR17               | /*  0x00020000 Configure Rising edge trigger for line 17   */\\
      0 * EXTI_RTSR_TR18                 /*  0x00040000 Configure Rising edge trigger for line 18   */\\
    )

    #define INIT_EXTI_FTSR       (     \\
      0 * EXTI_FTSR_TR0                | /*  0x00000001 Configure Falling edge trigger for line 0   */\\
      0 * EXTI_FTSR_TR1                | /*  0x00000002 Configure Falling edge trigger for line 1   */\\
      0 * EXTI_FTSR_TR2                | /*  0x00000004 Configure Falling edge trigger for line 2   */\\
      0 * EXTI_FTSR_TR3                | /*  0x00000008 Configure Falling edge trigger for line 3   */\\
      0 * EXTI_FTSR_TR4                | /*  0x00000010 Configure Falling edge trigger for line 4   */\\
      0 * EXTI_FTSR_TR5                | /*  0x00000020 Configure Falling edge trigger for line 5   */\\
      0 * EXTI_FTSR_TR6                | /*  0x00000040 Configure Falling edge trigger for line 6   */\\
      0 * EXTI_FTSR_TR7                | /*  0x00000080 Configure Falling edge trigger for line 7   */\\
      1 * EXTI_FTSR_TR8                | /*  0x00000100 Configure Falling edge trigger for line 8   */\\
      0 * EXTI_FTSR_TR9                | /*  0x00000200 Configure Falling edge trigger for line 9   */\\
      0 * EXTI_FTSR_TR10               | /*  0x00000400 Configure Falling edge trigger for line 10  */\\
      0 * EXTI_FTSR_TR11               | /*  0x00000800 Configure Falling edge trigger for line 11  */\\
      0 * EXTI_FTSR_TR12               | /*  0x00001000 Configure Falling edge trigger for line 12  */\\
      0 * EXTI_FTSR_TR13               | /*  0x00002000 Configure Falling edge trigger for line 13  */\\
      0 * EXTI_FTSR_TR14               | /*  0x00004000 Configure Falling edge trigger for line 14  */\\
      0 * EXTI_FTSR_TR15               | /*  0x00008000 Configure Falling edge trigger for line 15  */\\
      0 * EXTI_FTSR_TR16               | /*  0x00010000 Configure Falling edge trigger for line 16  */\\
      0 * EXTI_FTSR_TR17               | /*  0x00020000 Configure Falling edge trigger for line 17  */\\
      0 * EXTI_FTSR_TR18                 /*  0x00040000 Configure Falling edge trigger for line 18  */\\
    )

    #if INIT_AFIO_EXTICR_0
      AFIO->EXTICR[0] = INIT_AFIO_EXTICR_0;
    #endif

    #if INIT_AFIO_EXTICR_1
      AFIO->EXTICR[1] = INIT_AFIO_EXTICR_1;
    #endif

    #if INIT_AFIO_EXTICR_2
      AFIO->EXTICR[2] = INIT_AFIO_EXTICR_2;
    #endif

    #if INIT_AFIO_EXTICR_3
      AFIO->EXTICR[3] = INIT_AFIO_EXTICR_3;
    #endif

    #if INIT_EXTI_IMR
      EXTI->IMR = INIT_EXTI_IMR;
    #endif

    #if INIT_EXTI_RTSR
      EXTI->RTSR = INIT_EXTI_RTSR;
    #endif

    #if INIT_EXTI_FTSR
      EXTI->FTSR = INIT_EXTI_FTSR;
    #endif

    NVIC_SetPriority(EXTI9_5_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
    NVIC_ClearPendingIRQ(EXTI9_5_IRQn);
    NVIC_EnableIRQ(EXTI9_5_IRQn);
  #endif

  #if RTC_EN

    SET_REG_BIT(PWR->CR, PWR_CR_DBP);                         /* Disable Backup Domain write prot.  */

    if (0 == READ_REG_BIT(RCC->BDCR, RCC_BDCR_RTCEN)) {

      #if LSE_EN
        SET_REG_BIT(RCC->BDCR, RCC_BDCR_LSEON);               /* Enable LSE oscillator              */
        while(!READ_REG_BIT(RCC->BDCR, RCC_BDCR_LSERDY)) {  } /* Wait untill LSE becomes stable     */
        SET_REG_BIT(RCC->BDCR, RCC_BDCR_RTCSEL_LSE);          /* Use LSE as RTC clock               */
      #elif HSE_EN
        RCC->BDCR = RCC_BDCR_RTCSEL_HSE;                      /* Use (HSE / 128) as RTC clock       */
      #else
        SET_REG_BIT(RCC->CSR, RCC_CSR_LSION);                 /* Enable LSI oscillator              */
        while(!READ_REG_BIT(RCC->CSR, RCC_CSR_LSIRDY)) {  }   /* Wait untill LSE becomes stable     */
        SET_REG_BIT(RCC->BDCR, RCC_BDCR_RTCSEL_LSI);          /* Use LSI as RTC clock               */
      #endif

      SET_REG_BIT(RCC->BDCR, RCC_BDCR_RTCEN);                 /* Enable RTC peripheral              */
                                                                                                    /*
        Configuration procedure
        =======================
        1. Poll RTOFF, wait until its value goes to '1'
        2. Set the CNF bit to enter configuration mode
        3. Write to one or more RTC registers
        4. Clear the CNF bit to exit configuration mode
        5. Poll RTOFF, wait until its value goes to '1' to check the end of the write operation.

        The write operation only executes when the CNF bit is cleared; it takes at least three
        RTCCLK cycles to complete.                                                                  */

      while(!READ_REG_BIT(RTC->CRL, RTC_CRL_RTOFF)) { }       /* 1. Wait till write op. completes   */
      SET_REG_BIT(RTC->CRL, RTC_CRL_CNF);                     /* 2. Enter configuration mode        */
      #if LSE_EN                                              /* 3. Set RTC clock prescaler         */
                                                                                                    /*
                  Note: If the input clock frequency (fRTCCLK) is 32.768 kHz, write 7FFFh in this
                        register to get a signal period of 1 second.
                                                                                                    */
        RTC->PRLL = 0x7FFF;                                   /* 32768 / (32767 + 1) = 1            */
      #elif HSE_EN
        RTC->PRLL = 0xF423;                                   /* (HSE / 128) / (62499 + 1) = 1      */
      #else
        RTC->PRLL = 0x9CC0; // 0x9C3F                         /* LSI / (39999 + 1) = 1              */
      #endif

    } else {

      #if !LSE_EN && !HSE_EN && !IWDG_EN

        /* if LSI is used as RTC clock source the oscillator has to be started after system reset   */

        SET_REG_BIT(RCC->CSR, RCC_CSR_LSION);                 /* Enable LSI oscillator              */
        while(!READ_REG_BIT(RCC->CSR, RCC_CSR_LSIRDY)) {  }   /* Wait untill LSI becomes stable     */

      #endif
    }

    RTC->CRH = (
      RTC_CRH_ALRIE   |                                       /* Enable RTC Alarm interrupt         */
      RTC_CRH_SECIE                                           /* Enable RTC Second interrupt        */
    );

    /* 4. The write operation is executed when the CNF bit is reset by software after has been set. */
    CLEAR_REG_BIT(RTC->CRL, RTC_CRL_CNF);

    /* 5. */
    while(!READ_REG_BIT(RTC->CRL, RTC_CRL_RTOFF)) {
      /* wait until the last write operation completes */
    }

    /* Note: If the HSE divided by 128 is used as the RTC clock, this bit must remain set to 1.     */
    #if LSE_EN || !HSE_EN
      CLEAR_REG_BIT(PWR->CR, PWR_CR_DBP);                     /* Restore Backup Domain write prot.  */
    #endif

    #if RNG_EN && !ADC_EN
      CRC->DR = rtc_read_counter();
      srnd(prnd());
    #endif

    NVIC_SetPriority(RTC_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
    NVIC_ClearPendingIRQ(RTC_IRQn);
    NVIC_EnableIRQ(RTC_IRQn);

    /* EXTI line 17 is connected to the RTC Alarm event  */

    /* Configure exti and nvic for RTC IT                */
    /* (13) unmask line 17                               */
    /* (14) Rising edge for line 17                      */
    /* (15) Clear pending request line 17                */

    /* (16) Set priority                                 */
    /* (17) Enable RTC_IRQn                              */


    SET_REG_BIT(EXTI->IMR, EXTI_IMR_MR17);       /* (13) */
    SET_REG_BIT(EXTI->RTSR, EXTI_RTSR_TR17);     /* (14) */
    SET_REG_BIT(EXTI->PR, EXTI_PR_PR17);

    NVIC_SetPriority(RTC_Alarm_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
    NVIC_ClearPendingIRQ(RTC_Alarm_IRQn);
    NVIC_EnableIRQ(RTC_Alarm_IRQn);                           /* Enable RTC Alarm EXTI Interrupt    */

  #endif /* RTC_EN */

  #if WWDG_EN

    NVIC_SetPriority(WWDG_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
    NVIC_ClearPendingIRQ(WWDG_IRQn);
    NVIC_EnableIRQ(WWDG_IRQn);

    WWDG->CR = (                         /* 0x40002C00: WWDG Control register                       */
      WWDG_CR_WDGA            |          /* When WDGA=1, WWDG reset is enabled                      */
      WWDG_COUNTER                       /* 7-bit counter (MSB to LSB).                             */
    );                                   /* It is decremented every                                 */
                                         /* 4096 * 2 ^ WDGTB[1:0] PCLK1 cycles                      */
                                         /* A reset is produced when it rolls over from             */
                                         /* 0x40 to 0x3F (T6 becomes cleared)                       */

    WWDG->CFR = (                        /* 0x40002C04: WWDG Configuration register                 */
      1 * WWDG_CFR_EWI        |          /* Early wakeup interrupt                                  */
      1 * WWDG_CFR_WDGTB_0    |          /* Timer base bit 0                                        */
      1 * WWDG_CFR_WDGTB_1    |          /* Timer base bit 1                                        */
      1 * WWDG_WINDOW                    /* Watchdoeg Window                                        */
    );
  #endif

  SystemCoreClockUpdate();

}  /* init() */

#define HEX(NIBBLE) (((NIBBLE) < 10) ? (NIBBLE) + '0' : (NIBBLE) + '7')

#if USART_EN
  __STATIC_INLINE void uputc(const char c) {
    /*** Send char using USART1 ***/
    while (!READ_REG_BIT(USART1->SR, USART_SR_TXE)) {}        /* Wait until TX reg becomes empty    */
    USART1->DR = c;
  }

  __STATIC_INLINE void uputs(const char *c) {
    /*** Send string using UART ***/
    while(*c) {
      uputc(*c++);
    }
  }

  __STATIC_INLINE void uput_x(const uint8_t c) {
    /*** Convert a nibble to HEX and send it via UART ***/
    uputc(HEX(c));
  }

  __STATIC_INLINE void uputx(const uint8_t c) {
    /* Convert a byte to HEX and send it via UART */
    uput_x(c >> 4);
    uput_x(c & 0x0F);
  }

  #define uprintf(...) do{char _[200]; snprintf(_, sizeof(_), __VA_ARGS__); uputs(_);}while(0)
#else
  #define uprintf(...)
#endif

#if I2C_EN

  #define I2C_TIMEOUT     10
  #define I2C_ERR_TIMEOUT 1
  #define I2C_ERROR       (                                                            \\
                            I2C_SR1_BERR  |  /*  Bus Error            (0x00000100)   */\\
                            I2C_SR1_ARLO  |  /*  Arbitration Lost     (0x00000200)   */\\
                            I2C_SR1_AF    |  /*  Acknowledge Failure  (0x00000400)   */\\
                            I2C_SR1_OVR      /*  Overrun/Underrun     (0x00000800)   */\\
                          )

  __STATIC_INLINE ErrorStatus i2c_check(const unsigned bitFlag) {
    extern unsigned short i2c_status;
    unsigned t_out = I2C_TIMEOUT;
    (void) SysTick->CTRL;

    while((I2C1->SR1 & bitFlag) == 0) {
      t_out -= GET_TICK();
      if (t_out == 0) {
        i2c_status |= I2C_ERR_TIMEOUT;
        return ERROR;
      }

      {
        unsigned e_status = I2C1->SR1 & I2C_ERROR;
        if (e_status) {
          i2c_status = (unsigned short)e_status;
          return ERROR;
        }
      }
    }

    return SUCCESS;

  }  /* i2c_check() */


  __STATIC_INLINE ErrorStatus i2c_write(const char addr, const char *data, unsigned len) {
    I2C1->CR1 = I2C_CR1_START | I2C_CR1_ACK | I2C_CR1_PE;
    if (i2c_check(I2C_SR1_SB) == ERROR) return ERROR;

    I2C1->DR = (unsigned) addr << 1;
    if (i2c_check(I2C_SR1_ADDR) == ERROR) return ERROR;

    (void) I2C1->SR2;

    for(unsigned i = 0; i < len; i++) {
      if (i2c_check(I2C_SR1_TXE) == ERROR) return ERROR;
      I2C1->DR = data[i];
    }

    if (i2c_check(I2C_SR1_BTF) == ERROR) return ERROR;

    I2C1->CR1 = I2C_CR1_STOP | I2C_CR1_ACK | I2C_CR1_PE;
    return (ErrorStatus)(I2C1->SR1 & I2C_ERROR);

  }  /* i2c_write() */


  __STATIC_INLINE ErrorStatus i2c_read(const char addr, char *data, unsigned len) {

    I2C1->CR1 = I2C_CR1_START | I2C_CR1_ACK | I2C_CR1_PE;
    if (i2c_check(I2C_SR1_SB) == ERROR) return ERROR;

    I2C1->DR = (char)(addr << 1) + 1;
    if (i2c_check(I2C_SR1_ADDR) == ERROR) return ERROR;
    if (len == 1) I2C1->CR1 = I2C_CR1_PE;                 /* reset ACK bit              */

    (void) I2C1->SR2;

    for(unsigned i = 0; i < len; i++) {
      if (i == len - 1) I2C1->CR1 = I2C_CR1_PE;           /* reset ACK bit              */
      if (i2c_check(I2C_SR1_RXNE) == ERROR) return ERROR;
      data[i] = (char) I2C1->DR;
    }

    if (i2c_check(I2C_SR1_BTF) == ERROR) return ERROR;
    I2C1->CR1 = I2C_CR1_STOP | I2C_CR1_ACK | I2C_CR1_PE;

    return (ErrorStatus)(I2C1->SR1 & I2C_ERROR);

  }  /* i2c_read() */


  __STATIC_INLINE ErrorStatus i2c_read_reg(const char addr, char *data, char reg, unsigned len) {
    I2C1->CR1 = I2C_CR1_START | I2C_CR1_ACK | I2C_CR1_PE; /* generate START             */
    if (i2c_check(I2C_SR1_SB) == ERROR) return ERROR;

    I2C1->DR = (unsigned) addr << 1;                      /* send slave address         */
    if (i2c_check(I2C_SR1_ADDR) == ERROR) return ERROR;

    (void) I2C1->SR2;                                     /* dummy read status register */
    if (i2c_check(I2C_SR1_TXE) == ERROR) return ERROR;

    I2C1->DR = reg;                                       /* send register number       */
    if (i2c_check(I2C_SR1_BTF) == ERROR) return ERROR;

    I2C1->CR1 = I2C_CR1_START | I2C_CR1_ACK | I2C_CR1_PE; /* generate RE-START          */
    if (i2c_check(I2C_SR1_SB) == ERROR) return ERROR;

    I2C1->DR = (char)(addr << 1) + 1;                     /* send slave addr + read req */
    if (i2c_check(I2C_SR1_ADDR) == ERROR) return ERROR;

    if (len == 1) I2C1->CR1 = I2C_CR1_PE;                 /* reset ACK bit              */

    (void) I2C1->SR2;                                     /* dummy read status register */

    for(unsigned i = 0; i < len; i++) {
      if (i == len - 1) I2C1->CR1 = I2C_CR1_PE;           /* reset ACK bit              */
      if (i2c_check(I2C_SR1_RXNE) == ERROR) return ERROR;
      data[i] = (char) I2C1->DR;                          /* store received data        */
    }

    if (i2c_check(I2C_SR1_BTF) == ERROR) return ERROR;
    I2C1->CR1 = I2C_CR1_STOP | I2C_CR1_ACK | I2C_CR1_PE;  /* generate STOP              */

    return (ErrorStatus)(I2C1->SR1 & I2C_ERROR);

  }  /* i2c_read_reg() */

#endif


#if defined(__GNUC__) && ! defined(__clang__)
  void _close_r(void){} void _close(void){} void _lseek_r(void){} void _lseek(void){} void _read_r(void){} void _read(void){} void _write_r(void){}
#endif


#ifdef __cplusplus
}
#endif

#endif /* __MAIN_H */
MAIN_H

#
# generate main.c
#

cat <<MAIN_C >main.c
#include <stdio.h>
#include <string.h>
#include "main.h"

static void demo(void);

int main(void) {

  init();

  demo();

} /* main() */


#if BTN_EN
  static volatile unsigned button_state;
  static void button_pressed(unsigned btn_no) {
    (void) btn_no;
  }
  static void button_released(unsigned btn_no) {
    (void) btn_no;
  }
#endif


void SysTick_Handler(void) {

  #if TIM2_EN && DMA_EN
  #else
    static uint16_t t;              // 0…999
    t = (t + 1) % 1000;             // 1 ms roll-over
    // active slice: 0…179 ms  (3x30 ms on + 3x30 ms off)
    if (t < 180) PC.BSRR = ((t / 30) & 1) * GPIO_BSRR_BS13 | GPIO_BSRR_BR13;
  #endif

  #if BTN_EN
    enum {CURRENT = 0, PREVIOUS = 1, TOTAL = 2};
    static unsigned btn[TOTAL][TOTAL] = {{UINT32_MAX, UINT32_MAX}, {UINT32_MAX, UINT32_MAX}};

    btn[0][CURRENT] = (btn[0][CURRENT] << 1) | READ_REG_BIT(PB.IDR, GPIO_IDR_IDR0);
    btn[1][CURRENT] = (btn[1][CURRENT] << 1) | READ_REG_BIT(PB.IDR, GPIO_IDR_IDR1);

    if ((btn[0][CURRENT] == 0) && (btn[0][PREVIOUS] != 0)) {
      SET_MEM_BIT(button_state, BUTTON_1_PRESSED);
      button_pressed(0);
    }
    if ((btn[1][CURRENT] == 0) && (btn[1][PREVIOUS] != 0)) {
      SET_MEM_BIT(button_state, BUTTON_2_PRESSED);
      button_pressed(1);
    }
    if ((btn[0][CURRENT] == UINT32_MAX) && (btn[0][PREVIOUS] != UINT32_MAX)) {
      SET_MEM_BIT(button_state, BUTTON_1_RELEASED);
      button_released(0);
    }
    if ((btn[1][CURRENT] == UINT32_MAX) && (btn[1][PREVIOUS] != UINT32_MAX)) {
      SET_MEM_BIT(button_state, BUTTON_2_RELEASED);
      button_released(1);
    }
    btn[0][PREVIOUS] = btn[0][CURRENT];
    btn[1][PREVIOUS] = btn[1][CURRENT];
  #endif
} /* SysTick_Handler() */


#if RTC_EN
  static volatile unsigned rtc_flag;

  void RTC_IRQHandler(void) {                   /* RTC global interrupt handler  */

    if (READ_REG_BIT(RT.CRL, RTC_CRL_ALRF)) {
      CLEAR_REG_BIT(RT.CRL, RTC_CRL_ALRF);
      SET_MEM_BIT(rtc_flag, RTC_CRL_ALRF);
    }

    if (READ_REG_BIT(RT.CRL, RTC_CRL_SECF)) {
      CLEAR_REG_BIT(RT.CRL, RTC_CRL_SECF);
      SET_MEM_BIT(rtc_flag, RTC_CRL_SECF);
    }

  } /* RTC_IRQHandler() */

  void RTC_Alarm_IRQHandler(void) {             /* RTC alarm interrupt handler   */

    if (READ_REG_BIT(E.PR, EXTI_PR_PR17)) {
      SET_REG_BIT(E.PR, EXTI_PR_PR17);
      SET_MEM_BIT(rtc_flag, EXTI_PR_PR17);
    }

  } /* RTC_Alarm_IRQHandler() */
#endif


#if TIM2_EN
  static volatile unsigned tim2_counter;

  void TIM2_IRQHandler(void) {

    if (READ_REG_BIT(T2.SR, TIM_SR_UIF)) {
      CLEAR_REG_BIT(T2.SR, TIM_SR_UIF);
    } else if (READ_REG_BIT(T2.SR, TIM_SR_CC1IF)) {
      CLEAR_REG_BIT(T2.SR, TIM_SR_CC1IF);
    } else if (READ_REG_BIT(T2.SR, TIM_SR_CC2IF)) {
      CLEAR_REG_BIT(T2.SR, TIM_SR_CC2IF);
    } else if (READ_REG_BIT(T2.SR, TIM_SR_CC3IF)) {
      CLEAR_REG_BIT(T2.SR, TIM_SR_CC3IF);
    } else if (READ_REG_BIT(T2.SR, TIM_SR_CC4IF)) {
      CLEAR_REG_BIT(T2.SR, TIM_SR_CC4IF);
    }
    tim2_counter++;
  } /* TIM2_IRQHandler() */
#endif


#if ADC_EN
  void ADC1_2_IRQHandler(void) {
    A1.SR = 0;
  } /* ADC1_2_IRQHandler() */
#endif


#if EXTI_EN
  void EXTI9_5_IRQHandler(void) {                               /* EXTI line 8 interrupt handler      */
    if (READ_REG_BIT(E.PR, EXTI_PR_PR8)) {
      SET_REG_BIT(E.PR, EXTI_PR_PR8);
    }
  } /* EXTI9_5_IRQHandler() */
#endif


#if WWDG_EN
  void WWDG_IRQHandler(void) {
    W.SR = 0;                                                   /* 0x40002C08: WWDG Status register   */
    W.CR = 0x7F;                                                /* 0x40002C00: WWDG Control register  */
  } /* WWDG_IRQHandler() */
#endif


#if !defined NO_HF_IRQ
  void __NO_RETURN HardFault_Handler(void) {
    for(;;) {
      SW_PIN(C, 13, DOWN);
      DELAY_MS(60);
      SW_PIN(C, 13, UP);
      DELAY_MS(60);
    }
  } /* HardFault_Handler() */
#endif


#if I2C_EN
  unsigned short i2c_status = 0;
#endif


static void demo(void) {

  #if FLASH_EN
    /* Union variable with string initializer */
    union {
        char str[64];           /* String storage */
        uint16_t halfwords[32]; /* Same memory as half-words */
    } test_data = {
        .str = "Just a test string to write to the last FLASH page."
    };
    
    /* Calculate string length */
    const unsigned str_len = strlen(test_data.str) + 1;  /* Include '\0' */
    const unsigned write_len = (str_len + 1) & ~1u;      /* Round up to even */
    
    /* Write to Flash using halfwords */
    write2flash(test_data.halfwords, write_len);

    #if defined LOCK_FIRMWARE && LOCK_FIRMWARE != 0
      if (!READ_REG_BIT(F.OBR, FLASH_OBR_RDPRT)) {             /* Check RDP level status            */
        lock_firmware(NULL, NULL);                             /* Enable read- and write-protect    */
      }
    #endif
  #endif

  #if RTC_EN
    if (RT.CNTL + RT.CNTH == 0) {
      rtc_set_counter(1645568542);     /* Epoch timestamp 1645568542: Tue, 22 Feb 2022 22:22:22 GMT */
    }
    rtc_set_alarm(rtc_read_counter() + 30);
  #endif

  {
    extern const char *build_msg;
    #if USART_EN
      #if WWDG_EN
        if ((W.CR & WWDG_CR_T) < WWDG_WINDOW) {
          W.CR = WWDG_COUNTER;   /* RESET WWDG */
        }
      #endif
      #if DMA_EN
        D14.CCR = 0;
        D14.CNDTR = strlen(build_msg);   /* 0x40020048: */
        D14.CMAR = (unsigned) build_msg; /* 0x40020050: */
        D14.CCR = DMA1_Channel4_CCR;     /* 0x40020044: */
      #else
        uputs(build_msg);
      #endif
    #else
      (void) build_msg;
    #endif
  }

#if USART_EN || SPI_EN || I2C_EN || BTN_EN || RTC_EN || TIM2_EN || CRC_EN || ADC_EN || RNG_EN
  for(int i = 0; i <= INT32_MAX;) {
    union {
      char c[UINT8_MAX + 1];
      unsigned u[(UINT8_MAX + 1) / sizeof(unsigned)];  /* used for word access */
    } buf;

    #define BUF buf.c + i, sizeof(buf) - (size_t)i

    int j = 1000;
    do {

      // #if ADC_EN
      //   adc_data = (adc_data << 1) | adc_get_random_bit();
      // #endif

      #if RTC_EN
        if (READ_MEM_BIT(rtc_flag, RTC_CRL_SECF)) {
          CLEAR_MEM_BIT(rtc_flag, RTC_CRL_SECF);
          j = 0;
        }
      #else
        j -= GET_TICK();
      #endif
      #if WWDG_EN
        if ((W.CR & WWDG_CR_T) < WWDG_WINDOW) {
          W.CR = WWDG_COUNTER;   /* RESET WWDG */
        }
      #endif
    } while(j);

    i = snprintf(BUF, "Test@%uMHz", (uint8_t)(SystemCoreClock / 1000000));
    #if RNG_EN
      i += snprintf(BUF, " #0x%02X", rnd() % UINT8_MAX);
    #else
      {
        static char loop_counter;
        i += snprintf(BUF, " #0x%02X", ++loop_counter);
      }
    #endif
#else
  for(;;) {
    #define VOID_LOOP
    #if WWDG_EN
      if ((W.CR & WWDG_CR_T) < WWDG_WINDOW) {
        W.CR = WWDG_COUNTER;  /* RESET WWDG */
      }
    #endif
#endif

    #if I2C_EN
      {
        char x[0x13];
        i2c_read_reg(0x68, x, 0, sizeof(x));  /* Read DS1307/DS3231 register pool */
        if (i2c_status == 0) {
          i += snprintf(BUF, "; I2C: %02X:%02X:%02X", x[2], x[1], x[0]);
        } else {
          i += snprintf(BUF, "; I2C ERR: %04X", i2c_status);
        }
      }
    #endif

    #if SPI_EN
      {
        char rx;
        CS_LOW();
          spi_xfer(0x00);
          rx = spi_xfer(UINT8_MAX);
        CS_HIGH();
        i += snprintf(BUF, "; SPI: 0x%02X", rx);
      }
    #endif

    #if BTN_EN
      i += snprintf(BUF, "; KEY: %s/%s", (button_state & BUTTON_1_RELEASED) ? "ON" : "OFF",
                                         (button_state & BUTTON_2_RELEASED) ? "ON" : "OFF");
      button_state &= (unsigned)~(BUTTON_1_RELEASED | BUTTON_2_RELEASED);
    #endif

    #if RTC_EN
      {
        time_struct_t tm;
        char rtc_buf[10] = {0};
        unsigned rtc_counter = rtc_read_counter();

        unixtime_to_time(rtc_counter, &tm);

        if (READ_MEM_BIT(rtc_flag, EXTI_PR_PR17)) {
          CLEAR_MEM_BIT(rtc_flag, EXTI_PR_PR17);
          rtc_buf[0] = '/'; rtc_buf[1] = 'A';
        }
        if (READ_MEM_BIT(rtc_flag, RTC_CRL_ALRF)) {
          CLEAR_MEM_BIT(rtc_flag, RTC_CRL_ALRF);
          if (rtc_buf[0] == '/') {
            rtc_buf[2] = 'a';
          } else {
            rtc_buf[0] = '/'; rtc_buf[1] = 'a';
          }
          rtc_set_alarm(((RT.ALRH << 16) | RT.ALRL) + 30);
        }
        i += snprintf(BUF, "; RTC/%s: %02u.%02u.%02u %02u:%02u:%02u%s",
             ((R.BDCR & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL_LSE) ? "LSE" :
             ((R.BDCR & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL_HSE) ? "HSE" :
             ((R.BDCR & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL_LSI) ? "LSI" : "UNK",
             tm.day, tm.month, tm.year, tm.hour, tm.minute, tm.second, rtc_buf);
      }
    #endif

    #if TIM2_EN
      i += snprintf(BUF, "; TIM2: %08X", tim2_counter);
    #endif

    #if CRC_EN
      i += snprintf(BUF, "; CRC: %08X", crc32_zlib(buf.u, sizeof(buf.u)));
    #endif

    #if ADC_EN
      {
        short t;
        unsigned short v;
        get_adc_internals(&t, &v);
        i += snprintf(BUF, "; ADC: %u.%03u/%d", v / 1000, v % 1000, t);
      }
    #endif

    #if RNG_EN
      i += snprintf(BUF, "; RNG: %08X", rnd());
    #endif

    #if USART_EN
      #if DMA_EN
        i += snprintf(BUF, "\n");
        D14.CCR   = 0;                   /* 0x40020044: Disable DMA1 Ch 4                               */
        D14.CNDTR = (unsigned)i;         /* 0x40020048: Amount of data to send                          */
        D14.CMAR  = (unsigned)&buf;      /* 0x40020050: Data source address                             */
        D14.CCR   = DMA1_Channel4_CCR;   /* 0x40020044: Apply the channel config and start the transfer */
      #else
        buf.c[i++] = '\n';
        buf.c[i] = 0;
        uputs(buf.c);
      #endif
    #endif

    #if IWDG_EN
      I.KR = 0xAAAA;
    #endif
  }
} /* demo() */


#if RNG_EN
  static unsigned rnext; /* = 2463534242;  */
  unsigned rnd(void) {

  #if 0
    rnext = rnext * 1103515245 + 12345;
    return rnext / 65536 % (UINT16_MAX / 2 + 1);
  #else
    rnext ^= rnext << 13;
    rnext ^= rnext >> 17;
    rnext ^= rnext << 5;
    return rnext;
  #endif
  } /* rng() */

  void srnd(unsigned seed) {
    rnext = seed;
  } /* srng() */
#endif


// #if ADC_EN
//   static unsigned adc_data;
// #endif


#if DMA_EN
  const unsigned blink_pattern[30] = { /* Tripple flash per second */
    GPIO_BSRR_BR13, GPIO_BSRR_BS13,    /*   first flash            */
    GPIO_BSRR_BR13, GPIO_BSRR_BS13,    /*   second flash           */
    GPIO_BSRR_BR13, GPIO_BSRR_BS13     /*   third flash            */
  };
#endif


const char *build_msg  = ""
#if defined DEBUG
  "\\nThe firmware is built with following MACROs used:"
  #if defined(USE_HSE) && (USE_HSE != 0)
    " USE_HSE"
  #endif
  #if defined(USE_PLL) && (USE_PLL != 0)
    " USE_PLL"
  #endif
  #if defined(USE_LSE) && (USE_LSE != 0)
    " USE_LSE"
  #endif
  #if defined(USE_ADC) && (USE_ADC!= 0)
    " USE_ADC"
  #endif
  #if defined(USE_USART) && (USE_USART!= 0)
    " USE_USART"
  #endif
  #if defined(USE_I2C) && (USE_I2C != 0)
    " USE_I2C"
  #endif
  #if defined(USE_SPI) && (USE_SPI != 0)
    " USE_SPI"
  #endif
  #if defined(USE_BTN) && (USE_BTN != 0)
    " USE_BTN"
  #endif
  #if defined(USE_RTC) && (USE_RTC != 0)
    " USE_RTC"
  #endif
  #if defined(USE_TIM2) && (USE_TIM2 != 0)
    " USE_TIM2"
  #endif
  #if defined(USE_DMA) && (USE_DMA != 0)
    " USE_DMA"
  #endif
  #if defined(USE_CRC) && (USE_CRC != 0)
    " USE_CRC"
  #endif
  #if defined(USE_RNG) && (USE_RNG != 0)
    " USE_RNG"
  #endif
  #if defined(USE_IWDG) && (USE_IWDG != 0)
    " USE_IWDG"
  #endif
  #if defined(USE_WWDG) && (USE_WWDG != 0)
    " USE_WWDG"
  #endif
  #if defined(USE_EXTI) && (USE_EXTI != 0)
    " USE_EXTI"
  #endif
  #if defined(USE_FLASH) && (USE_FLASH != 0)
    " USE_FLASH"
  #endif
  #if defined(USE_USE_SWD) && (USE_USE_SWD != 0)
    " USE_SWD"
  #endif
  #if defined(USE_OVRCLK) && (USE_OVRCLK != 0)
    " OVRCLK"
  #endif
  #if !defined(__clang__)
  " ["__DATE__"]"
  #endif
  ".\n"
#endif
"\\n";

MAIN_C

#
# generate Makefile
#

cat <<MAKEFILE >Makefile
# Define the name of the project target and the build directory
TARGET = project
BUILD_DIR = build

ifeq (0, 1)
	# Set build directory based on make goals (debug or release)
	ifeq (\$(MAKECMDGOALS), debug)
    		BUILD_DIR := \$(addsuffix -debug, \$(BUILD_DIR))
	else
		BUILD_DIR := \$(addsuffix -release, \$(BUILD_DIR))
	endif
endif

# Define the C source files, assembly source file, linker script, and preprocessor definitions
SRC = main.c system_stm32f1xx.c
ASM = startup_stm32f103xb.s
LDS = STM32F103XB_FLASH.ld
MCU = -mcpu=cortex-m3 -mthumb
DEF = -DSTM32F103xB
INC = -I.
OPT = -O3 -g0 -flto

# Define additional preprocessor definitions based on conditional variables
USE := USE_ALL USE_PLL USE_HSE USE_LSE USE_ADC USE_USART USE_I2C USE_SPI 
USE += USE_BTN USE_RTC USE_TIM2 USE_DMA USE_CRC USE_RNG USE_IWDG USE_WWDG 
USE += USE_EXTI USE_FLASH USE_SWD OVRCLK
DEF += \$(strip \$(foreach def, \$(USE), \$(if \$(\$(def)), -D\$(def)=\$(\$(def)))))

# Define the toolchain prefix
TOOLCHAIN := \$(if \$(GCC_PATH),\$(GCC_PATH)/,)arm-none-eabi-

# Wrapper to quote paths with spaces
Q = \$(if \$(findstring \$(space),\$(1)),"\$(1)",\$(1))

CC = \$(call Q,\$(TOOLCHAIN)gcc)
LD = \$(call Q,\$(TOOLCHAIN)ld)
AS = \$(call Q,\$(TOOLCHAIN)gcc) -x assembler-with-cpp
CP = \$(call Q,\$(TOOLCHAIN)objcopy)
SZ = \$(call Q,\$(TOOLCHAIN)size)

# Define space for the Q function
space := \$(subst ,, )

# Define utility programs used for programming the device
HEX = \$(CP) -O ihex
BIN = \$(CP) -O binary -S

# Set additional compiler flags for dependencies and object file generation
FLAG = \$(MCU) \$(DEF) \$(INC) -Wall -Werror -Wextra -Wpedantic -fdata-sections -ffunction-sections

JLINK_FLAGS = -openprj./stm32f103cb.jflash -open\$(BUILD_DIR)/\$(TARGET).hex -hide -auto -exit -jflashlog./jflash.log

ifeq (\$(OS), Windows_NT)

    FLAG += -D WIN32
    ifeq (\$(PROCESSOR_ARCHITEW6432), AMD64)
        FLAG += -D AMD64
    else
        ifeq (\$(PROCESSOR_ARCHITECTURE), AMD64)
            FLAG += -D AMD64
        endif
        ifeq (\$(PROCESSOR_ARCHITECTURE), x86)
            FLAG += -D IA32
        endif
    endif

    STLINK = ST-LINK_CLI.exe
    STLINK_FLAGS = -c UR -V -P \$(BUILD_DIR)/\$(TARGET).hex -HardRst -Run

    JLINK = JFlash.Exe

else

    UNAME_S := \$(shell uname -s)
    ifeq (\$(UNAME_S), Linux)
        FLAG += -D LINUX
    endif
    ifeq (\$(UNAME_S), Darwin)
        FLAG += -D OSX
    endif
    UNAME_P := \$(shell uname -p)
    ifeq (\$(UNAME_P), x86_64)
        FLAG += -D AMD64
    endif
    ifneq (\$(filter %86, \$(UNAME_P)),)
        FLAG += -D IA32
    endif
    ifneq (\$(filter arm%, \$(UNAME_P)),)
        FLAG += -D ARM
    endif

    STLINK = st-flash
    STLINK_FLAGS = --reset --format ihex write \$(BUILD_DIR)/\$(TARGET).hex

    JLINK = JFlashExe

endif

# Set additional compiler flags for dependencies and object file generation
FLAG += -MMD -MP -MF \$(@:%.o=%.d)

# Define linker flags
LIB = -lc -lm -lnosys
LDFLAGS = \$(MCU) -specs=nano.specs -T\$(LDS) \$(LIB) -Wl,-Map=\$(BUILD_DIR)/\$(TARGET).map,--cref -Wl,--gc-sections

\$(info using GCC \$(shell \$(CC) -dumpfullversion), Linker \$(shell \$(LD) -v | sed 's/.* \([0-9]\+\.[0-9]\+\).*/\1/'))

# ---------- compiler / linker feature detection ----------
# Check if the linker supports --no-warn-rwx-segments.
LD_HAS_RWX := \$(shell \$(LD) --help 2>/dev/null | grep -- "--no-warn-rwx-segments")

ifneq (\$(LD_HAS_RWX),)
    LDFLAGS += -Wl,--no-warn-rwx-segments
endif

# Build all targets by default: the ELF binary, the HEX file, and the raw binary file
all: \$(BUILD_DIR)/\$(TARGET).elf \$(BUILD_DIR)/\$(TARGET).hex \$(BUILD_DIR)/\$(TARGET).bin

# Define the object files that need to be built from C and assembly source files
OBJ = \$(addprefix \$(BUILD_DIR)/,\$(notdir \$(SRC:.c=.o)))
vpath %.c \$(sort \$(dir \$(SRC))) # Set the search path for C source files

OBJ += \$(addprefix \$(BUILD_DIR)/,\$(notdir \$(ASM:.s=.o)))
vpath %.s \$(sort \$(dir \$(ASM))) # Set the search path for assembly source files

# Specify how to compile a C source file into an object file
\$(BUILD_DIR)/%.o: %.c Makefile | \$(BUILD_DIR)
	\$(CC) -c \$(FLAG) \$(OPT) \$(EXT) \$< -o \$@

# Specify how to compile an assembly source file into an object file
\$(BUILD_DIR)/%.o: %.s Makefile | \$(BUILD_DIR)
	\$(AS) -c \$(FLAG) \$(OPT) \$(EXT) -Wa,-a,-ad,-alms=\$(BUILD_DIR)/\$(notdir \$(<:.c=.lst)) \$< -o \$@

# Specify how to build the final executable file
\$(BUILD_DIR)/\$(TARGET).elf: \$(OBJ) Makefile
	\$(CC) \$(OBJ) \$(LDFLAGS) \$(OPT) \$(EXT) -o \$@
	\$(SZ) \$@

# Specify how to build the hex file using the elf file
\$(BUILD_DIR)/%.hex: \$(BUILD_DIR)/%.elf | \$(BUILD_DIR)
	\$(HEX) \$< \$@

# Specify how to build the bin file using the elf file
\$(BUILD_DIR)/%.bin: \$(BUILD_DIR)/%.elf | \$(BUILD_DIR)
	\$(BIN) \$< \$@

# Create the build directory if it doesn't exist
\$(BUILD_DIR):
	mkdir \$@

# Perform the 'test' target, which enables all conditional definitions and builds the project
test:  FLAG += -DUSE_ALL=1
test:  all

# Perform the 'debug' target, which enables SWD and debug symbols and builds the project
debug: OPT = -Og -g3 -gdwarf
debug: FLAG += -DUSE_SWD=1
debug: all

# Display compiler version information.
gccversion :
	@\$(CC) --version

# Program the device using st-link.
program: \$(BUILD_DIR)/\$(TARGET).hex
	\$(STLINK) \$(STLINK_FLAGS)

# Program the device using jlink.
jprogram: \$(BUILD_DIR)/\$(TARGET).hex
	\$(JLINK) \$(JLINK_FLAGS)

# Clean the build directory by removing all object files, dependency files, binaries, and map files
.PHONY: clean
clean:
	rm -fR \$(BUILD_DIR)

# Include the dependency files generated during compilation
-include \$(wildcard \$(BUILD_DIR)/*.d)

# *** EOF ***
MAKEFILE

cat <<DEBUG_JLINK >project.jdebug
void OnProjectLoad (void) {
  Project.SetDevice ("STM32F103C8");
  Project.SetHostIF ("USB", "");
  Project.SetTargetIF ("SWD");
  Project.SetTIFSpeed ("4 MHz");
  Project.AddSvdFile ("\$(InstallDir)/Config/CPU/Cortex-M3.svd");
  Project.AddSvdFile ("STM32F103xx.svd");
  File.Open ("build/project.elf");
}

void AfterTargetReset (void) {
  _SetupTarget();
}

void AfterTargetDownload (void) {
  _SetupTarget();
}

void _SetupTarget(void) {
  unsigned int SP;
  unsigned int PC;
  unsigned int VectorTableAddr;

  VectorTableAddr = Elf.GetBaseAddr();

  SP = Target.ReadU32(VectorTableAddr);
  if (SP != 0xFFFFFFFF) {
    Target.SetReg("SP", SP);
  }

  PC = Elf.GetEntryPointPC();
  if (PC != 0xFFFFFFFF) {
    Target.SetReg("PC", PC);
  } else {
    Util.Error("Project script error: failed to set up entry point PC", 1);
  }
}
DEBUG_JLINK

cat << JFLASH_CONFIG >stm32f103cb.jflash
  AppVersion = 70001
  FileVersion = 2
[GENERAL]
  aATEModuleSel[10] = 0,0,0,0,0,0,0,0,0,0
  ConnectMode = 0
  CurrentFile = "build/project.hex"
  DataFileSAddr = 0x00000000
  GUIMode = 0
  HostName = ""
  TargetIF = 1
  USBPort = 0
  USBSerialNo = 0x00000000
  UseATEModuleSelection = 0
[JTAG]
  IRLen = 0
  MultipleTargets = 0
  NumDevices = 0
  Speed0 = 4000
  Speed1 = 4000
  TAP_Number = 0
  UseAdaptive0 = 0
  UseAdaptive1 = 0
  UseMaxSpeed0 = 0
  UseMaxSpeed1 = 0
[CPU]
  NumInitSteps = 1
  InitStep0_Action = "Reset"
  InitStep0_Value0 = 0x00000000
  InitStep0_Value1 = 0x00000000
  InitStep0_Comment = "Reset and halt target"
  NumExitSteps = 0
  UseScriptFile = 0
  ScriptFile = ""
  UseRAM = 1
  RAMAddr = 0x20000000
  RAMSize = 0x00005000
  CheckCoreID = 1
  CoreID = 0x3BA00477
  CoreIDMask = 0x0F000FFF
  UseAutoSpeed = 0x00000001
  ClockSpeed = 0x00000000
  EndianMode = 0
  ChipName = "ST STM32F103CB (allow opt. bytes)"
[FLASH]
  aRangeSel[1] = 0-128
  BankName = "Internal flash"
  BankSelMode = 1
  BaseAddr = 0x06000000
  NumBanks = 1
[PRODUCTION]
  AutoPerformsDisconnect = 0
  AutoPerformsErase = 1
  AutoPerformsProgram = 1
  AutoPerformsSecure = 0
  AutoPerformsStartApp = 1
  AutoPerformsUnsecure = 0
  AutoPerformsVerify = 1
  EnableFixedVTref = 0
  EnableTargetPower = 0
  EraseType = 1
  FixedVTref = 0x00000CE4
  MonitorVTref = 0
  MonitorVTrefMax = 0x0000157C
  MonitorVTrefMin = 0x000003E8
  OverrideTimeouts = 0
  ProgramSN = 0
  SerialFile = ""
  SNAddr = 0x00000000
  SNInc = 0x00000001
  SNLen = 0x00000004
  SNListFile = ""
  SNValue = 0x00000001
  StartAppType = 0
  TargetPowerDelay = 0x00000014
  TimeoutErase = 0x00003A98
  TimeoutProgram = 0x00002710
  TimeoutVerify = 0x00002710
  VerifyType = 1
[PERFORMANCE]
  DisableSkipBlankDataOnProgram = 0x00000000
  PerfromBlankCheckPriorEraseChip = 0x00000001
  PerfromBlankCheckPriorEraseSelectedSectors = 0x00000001
JFLASH_CONFIG

for arg in "$@"; do
    if [ "$arg" = "opt" ]; then

        cat << STARTUP_S >startup_stm32f103xb.s
/**
 ******************************************************************************
 * @file      startup_stm32f103c8t6.s
 * @author    Your Name
 * @brief     STM32F103C8T6 startup code - Optimized version
 *            - Uses block transfer instructions (ldmia/stmia) for fast copy
 *            - Handles .data and .bss sections efficiently
 *            - No SystemInit() call (configure clocks in main if needed)
 ******************************************************************************
 */

.syntax unified              /* Use unified ARM/Thumb syntax */
.cpu cortex-m3              /* Target CPU: ARM Cortex-M3 */
.fpu softvfp                /* No hardware FPU, use software floating point */
.thumb                      /* Use Thumb instruction set */

/* Make vector table and default handler visible to linker */
.global g_pfnVectors
.global Default_Handler

/* Linker-provided symbols for memory sections */
.word _sidata               /* Start address of .data in Flash (source) */
.word _sdata                /* Start address of .data in SRAM (destination) */
.word _edata                /* End address of .data in SRAM */
.word _sbss                 /* Start address of .bss in SRAM */
.word _ebss                 /* End address of .bss in SRAM */

/* Special boot configuration for STM32 */
.equ  BootRAM, 0xF108F85F   /* Boot from RAM configuration value */

/**
 ******************************************************************************
 * @brief  Reset_Handler - Executed on system reset/power-up
 *
 * This is the first code that runs after the processor starts.
 * Execution flow:
 *   1. Copy initialized data from Flash to SRAM (.data section)
 *   2. Zero-fill uninitialized data in SRAM (.bss section)
 *   3. Jump to main() application code
 *   4. Trap in infinite loop if main() ever returns (should never happen)
 ******************************************************************************
 */
  .section .text.Reset_Handler
  .weak Reset_Handler
  .type Reset_Handler, %function

Reset_Handler:

/*----------------------------------------------------------------------------*/
/* STEP 1: Copy .data section from Flash to SRAM                              */
/*----------------------------------------------------------------------------*/
/* The .data section contains initialized global/static variables.            */
/* Their initial values are stored in Flash and must be copied to SRAM.       */
/*----------------------------------------------------------------------------*/

  ldr r0, =_sdata           /* R0 = Destination start address (SRAM) */
  ldr r1, =_edata           /* R1 = Destination end address (SRAM) */
  ldr r2, =_sidata          /* R2 = Source start address (Flash) */
  subs r3, r1, r0           /* R3 = Size of .data section in bytes */
  ble SkipDataCopy          /* Skip if .data is empty (size <= 0) */

/* Main copy loop: Process 32 bytes (8 words) per iteration using block transfer */
CopyDataInit:
  subs r3, r3, #32          /* Decrement counter by 32 bytes */
  blt CopyDataRemainder     /* If less than 32 bytes remain, handle remainder */
  ldmia r2!, {r4-r11}       /* Load 8 words (32 bytes) from Flash, auto-increment R2 */
  stmia r0!, {r4-r11}       /* Store 8 words (32 bytes) to SRAM, auto-increment R0 */
  b CopyDataInit            /* Continue main loop */

/* Handle remaining bytes when less than 32 bytes left */
CopyDataRemainder:
  adds r3, r3, #32          /* Restore the actual remainder count */
  cbz r3, SkipDataCopy      /* If remainder is zero, we're done */

/* Copy remainder word-by-word (4 bytes at a time) */
CopyDataWord:
  subs r3, r3, #4           /* Decrement counter by 4 bytes (1 word) */
  ldr r4, [r2], #4          /* Load 1 word from Flash, auto-increment R2 */
  str r4, [r0], #4          /* Store 1 word to SRAM, auto-increment R0 */
  bne CopyDataWord          /* Continue if more bytes remain */

SkipDataCopy:

/*----------------------------------------------------------------------------*/
/* STEP 2: Zero-fill .bss section in SRAM                                     */
/*----------------------------------------------------------------------------*/
/* The .bss section contains uninitialized global/static variables.           */
/* C standard requires these to be zero-initialized before main() is called.  */
/*----------------------------------------------------------------------------*/

  ldr r0, =_sbss            /* R0 = Start address of .bss section */
  ldr r1, =_ebss            /* R1 = End address of .bss section */
  subs r6, r1, r0           /* R6 = Size of .bss section in bytes */
  ble SkipBssZero           /* Skip if .bss is empty (size <= 0) */

  /* Initialize 8 registers with zero - done ONCE before loop for efficiency */
  movs r2, #0               /* R2 = 0 */
  movs r3, #0               /* R3 = 0 */
  movs r4, #0               /* R4 = 0 */
  movs r5, #0               /* R5 = 0 */
  movs r7, #0               /* R7 = 0 (skip R6, it's our counter) */
  movs r8, #0               /* R8 = 0 */
  movs r9, #0               /* R9 = 0 */
  movs r10, #0              /* R10 = 0 */

/* Main zeroing loop: Process 32 bytes (8 words) per iteration using block transfer */
FillZerobss:
  subs r6, r6, #32          /* Decrement counter by 32 bytes */
  blt FillZeroRemainder     /* If less than 32 bytes remain, handle remainder */
  stmia r0!, {r2-r5, r7-r10} /* Store 8 zero words (32 bytes) to SRAM, auto-increment R0 */
  b FillZerobss             /* Continue main loop */

/* Handle remaining bytes when less than 32 bytes left */
FillZeroRemainder:
  adds r6, r6, #32          /* Restore the actual remainder count */
  cbz r6, SkipBssZero       /* If remainder is zero, we're done */

/* Zero remainder word-by-word (4 bytes at a time) */
FillZeroWord:
  subs r6, r6, #4           /* Decrement counter by 4 bytes (1 word) */
  str r2, [r0], #4          /* Store zero to SRAM, auto-increment R0 */
  bne FillZeroWord          /* Continue if more bytes remain */

SkipBssZero:

/*----------------------------------------------------------------------------*/
/* STEP 3: Call main() function                                               */
/*----------------------------------------------------------------------------*/
/* At this point, the C runtime environment is fully initialized:             */
/*   - Stack pointer was set by hardware from vector table                    */
/*   - .data section is copied from Flash to SRAM                             */
/*   - .bss section is zero-initialized                                       */
/* Now it's safe to call the main application code.                           */
/*----------------------------------------------------------------------------*/

  bl main                   /* Branch with Link to main() function */

/*----------------------------------------------------------------------------*/
/* STEP 4: Trap if main() returns (should never happen in embedded systems)   */
/*----------------------------------------------------------------------------*/
/* In embedded systems, main() should never return. If it does, something     */
/* went wrong. We trap here in an infinite loop for debugging.                */
/*----------------------------------------------------------------------------*/

Infinite_Loop:
  b Infinite_Loop           /* Loop forever */
.size Reset_Handler, .-Reset_Handler

/**
 ******************************************************************************
 * @brief  Default_Handler - Default handler for all unhandled interrupts
 *
 * If an interrupt occurs and no specific handler is defined, execution
 * will trap here in an infinite loop. This helps catch unexpected interrupts
 * during development and debugging.
 ******************************************************************************
 */
    .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop_Default:
  b Infinite_Loop_Default   /* Trap unhandled interrupts here */
  .size Default_Handler, .-Default_Handler

/**
 ******************************************************************************
 * Interrupt Vector Table for STM32F103C8T6 (ARM Cortex-M3)
 *
 * This table MUST be placed at the start of Flash memory (address 0x08000000)
 * The processor uses this table to find interrupt handler addresses.
 *
 * Entry 0:  Initial Stack Pointer (loaded into SP on reset)
 * Entry 1:  Reset Handler (executed on power-up/reset)
 * Entry 2+: Exception and Interrupt Handlers (60+ entries for STM32F103)
 *
 * All handlers default to Default_Handler via weak aliases (see below)
 * You can override any handler by defining a function with the same name.
 ******************************************************************************
 */
  .section .isr_vector,"a",%progbits
  .type g_pfnVectors, %object
  .size g_pfnVectors, .-g_pfnVectors

g_pfnVectors:
  /* Cortex-M3 Core Exceptions */
  .word _estack                      /* 0: Initial Stack Pointer (top of RAM) */
  .word Reset_Handler                /* 1: Reset Handler */
  .word NMI_Handler                  /* 2: Non-Maskable Interrupt */
  .word HardFault_Handler            /* 3: Hard Fault (all unrecoverable errors) */
  .word MemManage_Handler            /* 4: Memory Management Fault */
  .word BusFault_Handler             /* 5: Bus Fault (memory access error) */
  .word UsageFault_Handler           /* 6: Usage Fault (undefined instruction, etc.) */
  .word 0                            /* 7: Reserved */
  .word 0                            /* 8: Reserved */
  .word 0                            /* 9: Reserved */
  .word 0                            /* 10: Reserved */
  .word SVC_Handler                  /* 11: Supervisor Call (used by RTOS) */
  .word DebugMon_Handler             /* 12: Debug Monitor */
  .word 0                            /* 13: Reserved */
  .word PendSV_Handler               /* 14: Pendable Service (used by RTOS) */
  .word SysTick_Handler              /* 15: System Tick Timer */
  
  /* STM32F103 Peripheral Interrupts */
  .word WWDG_IRQHandler              /* 16: Window Watchdog */
  .word PVD_IRQHandler               /* 17: Programmable Voltage Detector */
  .word TAMPER_IRQHandler            /* 18: Tamper (RTC intrusion detection) */
  .word RTC_IRQHandler               /* 19: Real-Time Clock */
  .word FLASH_IRQHandler             /* 20: Flash Memory */
  .word RCC_IRQHandler               /* 21: Reset and Clock Control */
  .word EXTI0_IRQHandler             /* 22: External Interrupt Line 0 */
  .word EXTI1_IRQHandler             /* 23: External Interrupt Line 1 */
  .word EXTI2_IRQHandler             /* 24: External Interrupt Line 2 */
  .word EXTI3_IRQHandler             /* 25: External Interrupt Line 3 */
  .word EXTI4_IRQHandler             /* 26: External Interrupt Line 4 */
  .word DMA1_Channel1_IRQHandler     /* 27: DMA1 Channel 1 */
  .word DMA1_Channel2_IRQHandler     /* 28: DMA1 Channel 2 */
  .word DMA1_Channel3_IRQHandler     /* 29: DMA1 Channel 3 */
  .word DMA1_Channel4_IRQHandler     /* 30: DMA1 Channel 4 */
  .word DMA1_Channel5_IRQHandler     /* 31: DMA1 Channel 5 */
  .word DMA1_Channel6_IRQHandler     /* 32: DMA1 Channel 6 */
  .word DMA1_Channel7_IRQHandler     /* 33: DMA1 Channel 7 */
  .word ADC1_2_IRQHandler            /* 34: ADC1 and ADC2 */
  .word USB_HP_CAN1_TX_IRQHandler    /* 35: USB High Priority or CAN TX */
  .word USB_LP_CAN1_RX0_IRQHandler   /* 36: USB Low Priority or CAN RX0 */
  .word CAN1_RX1_IRQHandler          /* 37: CAN RX1 */
  .word CAN1_SCE_IRQHandler          /* 38: CAN SCE (Status Change Error) */
  .word EXTI9_5_IRQHandler           /* 39: External Interrupts 9-5 */
  .word TIM1_BRK_IRQHandler          /* 40: Timer 1 Break */
  .word TIM1_UP_IRQHandler           /* 41: Timer 1 Update */
  .word TIM1_TRG_COM_IRQHandler      /* 42: Timer 1 Trigger/Commutation */
  .word TIM1_CC_IRQHandler           /* 43: Timer 1 Capture/Compare */
  .word TIM2_IRQHandler              /* 44: Timer 2 */
  .word TIM3_IRQHandler              /* 45: Timer 3 */
  .word TIM4_IRQHandler              /* 46: Timer 4 */
  .word I2C1_EV_IRQHandler           /* 47: I2C1 Event */
  .word I2C1_ER_IRQHandler           /* 48: I2C1 Error */
  .word I2C2_EV_IRQHandler           /* 49: I2C2 Event */
  .word I2C2_ER_IRQHandler           /* 50: I2C2 Error */
  .word SPI1_IRQHandler              /* 51: SPI1 */
  .word SPI2_IRQHandler              /* 52: SPI2 */
  .word USART1_IRQHandler            /* 53: USART1 */
  .word USART2_IRQHandler            /* 54: USART2 */
  .word USART3_IRQHandler            /* 55: USART3 */
  .word EXTI15_10_IRQHandler         /* 56: External Interrupts 15-10 */
  .word RTC_Alarm_IRQHandler         /* 57: RTC Alarm through EXTI */
  .word USBWakeUp_IRQHandler         /* 58: USB Wakeup from suspend */
  .word 0                            /* 59: Reserved */
  .word 0                            /* 60: Reserved */
  .word 0                            /* 61: Reserved */
  .word 0                            /* 62: Reserved */
  .word 0                            /* 63: Reserved */
  .word 0                            /* 64: Reserved */
  .word 0                            /* 65: Reserved */
  .word BootRAM                      /* 66: Boot from RAM configuration */

/**
 ******************************************************************************
 * Weak aliases for interrupt handlers
 *
 * All interrupt handlers are "weakly" aliased to Default_Handler.
 * This means if you don't define a specific handler, it will use
 * Default_Handler by default.
 *
 * To implement your own handler, simply define a function with the same
 * name (e.g., void TIM2_IRQHandler(void)) and it will override the weak alias.
 ******************************************************************************
 */

/* Cortex-M3 Core Exception Handlers */
  .weak NMI_Handler
  .thumb_set NMI_Handler,Default_Handler

  .weak HardFault_Handler
  .thumb_set HardFault_Handler,Default_Handler

  .weak MemManage_Handler
  .thumb_set MemManage_Handler,Default_Handler

  .weak BusFault_Handler
  .thumb_set BusFault_Handler,Default_Handler

  .weak UsageFault_Handler
  .thumb_set UsageFault_Handler,Default_Handler

  .weak SVC_Handler
  .thumb_set SVC_Handler,Default_Handler

  .weak DebugMon_Handler
  .thumb_set DebugMon_Handler,Default_Handler

  .weak PendSV_Handler
  .thumb_set PendSV_Handler,Default_Handler

  .weak SysTick_Handler
  .thumb_set SysTick_Handler,Default_Handler

/* STM32F103 Peripheral Interrupt Handlers */
  .weak WWDG_IRQHandler
  .thumb_set WWDG_IRQHandler,Default_Handler

  .weak PVD_IRQHandler
  .thumb_set PVD_IRQHandler,Default_Handler

  .weak TAMPER_IRQHandler
  .thumb_set TAMPER_IRQHandler,Default_Handler

  .weak RTC_IRQHandler
  .thumb_set RTC_IRQHandler,Default_Handler

  .weak FLASH_IRQHandler
  .thumb_set FLASH_IRQHandler,Default_Handler

  .weak RCC_IRQHandler
  .thumb_set RCC_IRQHandler,Default_Handler

  .weak EXTI0_IRQHandler
  .thumb_set EXTI0_IRQHandler,Default_Handler

  .weak EXTI1_IRQHandler
  .thumb_set EXTI1_IRQHandler,Default_Handler

  .weak EXTI2_IRQHandler
  .thumb_set EXTI2_IRQHandler,Default_Handler

  .weak EXTI3_IRQHandler
  .thumb_set EXTI3_IRQHandler,Default_Handler

  .weak EXTI4_IRQHandler
  .thumb_set EXTI4_IRQHandler,Default_Handler

  .weak DMA1_Channel1_IRQHandler
  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler

  .weak DMA1_Channel2_IRQHandler
  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler

  .weak DMA1_Channel3_IRQHandler
  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler

  .weak DMA1_Channel4_IRQHandler
  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler

  .weak DMA1_Channel5_IRQHandler
  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler

  .weak DMA1_Channel6_IRQHandler
  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler

  .weak DMA1_Channel7_IRQHandler
  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler

  .weak ADC1_2_IRQHandler
  .thumb_set ADC1_2_IRQHandler,Default_Handler

  .weak USB_HP_CAN1_TX_IRQHandler
  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler

  .weak USB_LP_CAN1_RX0_IRQHandler
  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler

  .weak CAN1_RX1_IRQHandler
  .thumb_set CAN1_RX1_IRQHandler,Default_Handler

  .weak CAN1_SCE_IRQHandler
  .thumb_set CAN1_SCE_IRQHandler,Default_Handler

  .weak EXTI9_5_IRQHandler
  .thumb_set EXTI9_5_IRQHandler,Default_Handler

  .weak TIM1_BRK_IRQHandler
  .thumb_set TIM1_BRK_IRQHandler,Default_Handler

  .weak TIM1_UP_IRQHandler
  .thumb_set TIM1_UP_IRQHandler,Default_Handler

  .weak TIM1_TRG_COM_IRQHandler
  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler

  .weak TIM1_CC_IRQHandler
  .thumb_set TIM1_CC_IRQHandler,Default_Handler

  .weak TIM2_IRQHandler
  .thumb_set TIM2_IRQHandler,Default_Handler

  .weak TIM3_IRQHandler
  .thumb_set TIM3_IRQHandler,Default_Handler

  .weak TIM4_IRQHandler
  .thumb_set TIM4_IRQHandler,Default_Handler

  .weak I2C1_EV_IRQHandler
  .thumb_set I2C1_EV_IRQHandler,Default_Handler

  .weak I2C1_ER_IRQHandler
  .thumb_set I2C1_ER_IRQHandler,Default_Handler

  .weak I2C2_EV_IRQHandler
  .thumb_set I2C2_EV_IRQHandler,Default_Handler

  .weak I2C2_ER_IRQHandler
  .thumb_set I2C2_ER_IRQHandler,Default_Handler

  .weak SPI1_IRQHandler
  .thumb_set SPI1_IRQHandler,Default_Handler

  .weak SPI2_IRQHandler
  .thumb_set SPI2_IRQHandler,Default_Handler

  .weak USART1_IRQHandler
  .thumb_set USART1_IRQHandler,Default_Handler

  .weak USART2_IRQHandler
  .thumb_set USART2_IRQHandler,Default_Handler

  .weak USART3_IRQHandler
  .thumb_set USART3_IRQHandler,Default_Handler

  .weak EXTI15_10_IRQHandler
  .thumb_set EXTI15_10_IRQHandler,Default_Handler

  .weak RTC_Alarm_IRQHandler
  .thumb_set RTC_Alarm_IRQHandler,Default_Handler

  .weak USBWakeUp_IRQHandler
  .thumb_set USBWakeUp_IRQHandler,Default_Handler

/**
 ******************************************************************************
 * End of startup code
 ******************************************************************************
 */
STARTUP_S

        cat << LINKER_SCRIPT >STM32F103XB_FLASH.ld
/*
*****************************************************************************
**  File        : STM32F103XB_FLASH.ld
**  Abstract    : Optimized Linker script for STM32F103xB
**                (128KByte FLASH, 20KByte RAM)
**  Context     : Pure C, No C++ Exceptions, Space Optimized
*****************************************************************************
*/

/* Entry Point */
ENTRY(Reset_Handler)

/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200;      /* required amount of heap  */
_Min_Stack_Size = 0x400;     /* required amount of stack */

/* Specify the memory areas */
MEMORY
{
  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
  RAM   (xrw)     : ORIGIN = 0x20000000, LENGTH = 20K
}

/* Highest address of the user mode stack */
/* Optimized: Automate calculation to always point to end of RAM */
_estack = ORIGIN(RAM) + LENGTH(RAM);

/* Define output sections */
SECTIONS
{
  /* The startup code goes first into FLASH */
  .isr_vector :
  {
    . = ALIGN(4);
    KEEP(*(.isr_vector)) /* Startup code */
    . = ALIGN(4);
  } >FLASH

  /* The program code and other data goes into FLASH */
  .text :
  {
    . = ALIGN(4);
    *(.text)           /* .text sections (code) */
    *(.text*)          /* .text* sections (code) */
    *(.glue_7)         /* glue arm to thumb code */
    *(.glue_7t)        /* glue thumb to arm code */
    *(.eh_frame)

    /* Optimization: Keep .init/.fini only if absolutely needed by libc */
    KEEP (*(.init))
    KEEP (*(.fini))

    . = ALIGN(4);
    _etext = .;        /* define a global symbols at end of code */
  } >FLASH

  /* Constant data goes into FLASH */
  .rodata :
  {
    . = ALIGN(4);
    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
    . = ALIGN(4);
  } >FLASH

  /* 
   * OPTIMIZATION FOR PURE C:
   * We discard C++ exception handling tables and constructor arrays.
   * If you later add C++, you must move these back to >FLASH.
   */
  /DISCARD/ :
  {
    *(.ARM.exidx*)     /* Exception index - saves space in C projects */
    *(.ARM.extab*)     /* Exception handling table */
    *(.init_array*)    /* C++ Constructors */
    *(.fini_array*)    /* C++ Destructors */
    *(.preinit_array*)
    *(.comment)        /* GCC compiler comments */
    *(.ARM.attributes) /* Optional: remove ARM attributes if not needed */
  }

  /* Used by the startup to initialize data */
  _sidata = LOADADDR(.data);

  /* Initialized data sections goes into RAM, load LMA copy after code */
  .data : 
  {
    . = ALIGN(4);
    _sdata = .;        /* create a global symbol at data start */
    *(.data)           /* .data sections */
    *(.data*)          /* .data* sections */

    . = ALIGN(4);
    _edata = .;        /* define a global symbol at data end */
  } >RAM AT> FLASH

  /* Uninitialized data section */
  .bss :
  {
    . = ALIGN(4);
    _sbss = .;         /* define a global symbol at bss start */
    __bss_start__ = _sbss;
    *(.bss)
    *(.bss*)
    *(COMMON)

    . = ALIGN(4);
    _ebss = .;         /* define a global symbol at bss end */
    __bss_end__ = _ebss;
  } >RAM

  /* User_heap_stack section, used to check that there is enough RAM left */
  ._user_heap_stack :
  {
    . = ALIGN(8);
    PROVIDE ( end = . );
    PROVIDE ( _end = . );
    . = . + _Min_Heap_Size;
    . = . + _Min_Stack_Size;
    . = ALIGN(8);
  } >RAM
}
LINKER_SCRIPT
        sed -i 's/^LDFLAGS = /&-nostartfiles /' Makefile
        break
    fi
done


#
# run 'make' utility
#

make test

echo
echo "type \"make program\" or \"make jprogram\" to download the firmware into a chip."