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Expand file tree Collapse file tree Original file line number Diff line number Diff line change @@ -16,18 +16,53 @@ Built as a hardware-verification portfolio project for HAV / DV internships.
1616
1717## Folder structure
1818
19- ├── rtl/ # DUTs (clean + buggy)
19+ ``` text
20+ memory-ctrl-verification/
21+ ├── .github/
22+ │ └── workflows/
23+ │ └── regression.yml
24+ ├── docs/
25+ │ ├── img/
26+ │ │ ├── bug_run_dashboard.png
27+ │ │ ├── clean_run_dashboard.png
28+ │ │ ├── waveform_addr7_bug.png
29+ │ │ └── waveform_reset.png
30+ │ ├── architecture.md
31+ │ ├── results_template.md
32+ │ └── verification_plan.md
33+ ├── reports/
34+ │ └── .gitkeep
35+ ├── rtl/
36+ │ ├── memory_ctrl.sv
37+ │ └── memory_ctrl_buggy.sv
38+ ├── scripts/
39+ │ ├── clean.ps1
40+ │ ├── run_simple.tcl
41+ │ ├── run_uvm.tcl
42+ │ └── run_uvm_bug.tcl
2043├── tb/
21- │ ├── simple/ # Original task-based testbench
22- │ └── uvm/ # UVM environment
23- ├── scripts/ # TCL + PowerShell automation
24- ├── tools/ # Python regression + dashboard
25- ├── reports/ # Generated logs + HTML report (gitignored)
26- ├── docs/ # Verification plan, architecture, results template
27- ├── .github/workflows/ # CI (Python checks; SV needs self-hosted runner)
28- ├── requirements.txt
29- └── README.md
30-
44+ │ ├── simple/
45+ │ │ ├── mem_test.sv
46+ │ │ └── tb_top.sv
47+ │ └── uvm/
48+ │ ├── mem_agent.sv
49+ │ ├── mem_base_test.sv
50+ │ ├── mem_coverage.sv
51+ │ ├── mem_driver.sv
52+ │ ├── mem_env.sv
53+ │ ├── mem_if.sv
54+ │ ├── mem_monitor.sv
55+ │ ├── mem_scoreboard.sv
56+ │ ├── mem_seq_item.sv
57+ │ ├── mem_sequence.sv
58+ │ ├── mem_uvm_pkg.sv
59+ │ └── tb_top_uvm.sv
60+ ├── tools/
61+ │ ├── dashboard.py
62+ │ └── regression.py
63+ ├── .gitignore
64+ ├── README.md
65+ └── requirements.txt
3166## Simulator requirements
3267
3368| Flow | Simulator |
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