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However, we encourage you to use our workload launch manager 'run_simulations' script as shown above, which will greatly simplify the simulation process and increase productivity.
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To understand what is going on and how to just run the simulator in isolation without the framework, read [this](https://github.com/accel-sim/accel-sim-framework/tree/dev/util/job_launching/README.md).
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3. **Accel-Sim Correlator**: A tool that matches, plots and correlates statistics from the performance model with real hardware statistics generated by profiling tools. To use the correlator, you must first generate hardware output and simulation statistics. To generate output from the GPU, use the scripts in [./util/hw_stats](./util/hw_stats).
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The Accel-Sim's performance model relies on GPGPU-Sim 4.0 Performance mopdel. We created new classes with "exec_" and "trace_" prefix that are inherited from gpgpu-sim performance model classes, then we moved some function implementations from the performance model to the new inherited classes using virtual functions. These functions are the ones that differ from exec-driven mode versus trace-driven mode. For example, when gpgpu-sim call the function "get_next_inst()", the exec_shader_core_ctx implementation will get the next instruction from the functional model, whereas the trace_shader_core_ctx will get the next inst from the traces.
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The Accel-Sim's performance model relies on GPGPU-Sim 4.0 performance model. We created new classes with "exec_" and "trace_" prefix that are inherited from gpgpu-sim performance model classes, then we moved some function implementations from the performance model to the new inherited classes using virtual functions. These functions are the ones that differ from exec-driven mode versus trace-driven mode. For example, when gpgpu-sim call the function "get_next_inst()", the exec_shader_core_ctx implementation will get the next instruction from the functional model, whereas the trace_shader_core_ctx will get the next inst from the traces.
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The blue blocks in the image are maintained in GPGPU-Sim 4.0 repo [here](https://github.com/gpgpu-sim/gpgpu-sim_distribution), whereas the green blocks are maintained by accel-sim in this repo.
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For each new GPU generation, we have to crease ISA_def file that specifies the SASS instructions. For now, we have created the ISA_def files for NVIDIA's Kepler, Pascal, Turing and Volta generations. Please see the directory [./trace-driven/ISA_Def](./trace-driven/ISA_Def).
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For each new GPU generation, we have to crease ISA_def file that specifies the SASS instructions. For now, we have created the ISA_def files for NVIDIA's Kepler, Pascal, Turing and Volta generations. Please see the directory [./ISA_Def](./ISA_Def).
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We were able to generate these files using the NVIDIA's CUDA Binary Utilities documentation from [here](https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html#instruction-set-ref).
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For more info on the Accel-Sim front-end and how to compile, please see "Accel-Sim SASS Frontend" entry in the main read-me page [here](https://github.com/accel-sim/accel-sim-framework/blob/dev/README.md).
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You do not need to clone the GPGPU-Sim 4.0 by your self. The [./setup_environment.sh](./setup_environment.sh) will clone the recent GPGPU-Sim model and integrate it with Accel-Sim. For more info on the Accel-Sim front-end and how to compile, please see "Accel-Sim SASS Frontend" entry in the main read-me page [here](https://github.com/accel-sim/accel-sim-framework/blob/dev/README.md).
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