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[mlir][dxsa] Add dcl_index_range instruction
Example: dxsa.dcl_index_range <type = input, components = 4, mask = <x, y, z, w>, index = [1]>, 3 Signed-off-by: Vladimir Shiryaev <tagolog@users.noreply.github.com>
1 parent 014c7b3 commit 92bc096

6 files changed

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mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td

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@@ -719,4 +719,22 @@ def DXSA_DclOutput : DXSA_Op<"dcl_output"> {
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let assemblyFormat = "$operand attr-dict";
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}
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def DXSA_DclIndexRange : DXSA_Op<"dcl_index_range"> {
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let summary = "declares a range of input or output registers to be indexed";
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let description = [{
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The `dxsa.dcl_index_range` operation declares a range of input or output
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registers to be indexed.
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Example:
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```mlir
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dxsa.dcl_index_range <type = output, components = 4, mask = <x>, index = [0]>, 4
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```
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}];
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let arguments = (ins DXSA_InlineOperandAttr:$operand,
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ConfinedAttr<I32Attr, [IntPositive]>:$count);
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let assemblyFormat = "$operand `,` $count attr-dict";
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let hasVerifier = 1;
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}
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#endif // DXSA_OPS

mlir/lib/Dialect/DXSA/IR/DXSA.cpp

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@@ -41,6 +41,19 @@ void DXSADialect::initialize() {
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#define GET_OP_CLASSES
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#include "mlir/Dialect/DXSA/IR/DXSAOps.cpp.inc"
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//===----------------------------------------------------------------------===//
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// Op verifiers
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//===----------------------------------------------------------------------===//
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LogicalResult DclIndexRange::verify() {
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auto operandType = getOperand().getType();
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if (operandType != InlineOperandType::input &&
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operandType != InlineOperandType::output)
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return emitOpError("operand must be an input or output register, got ")
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<< stringifyInlineOperandType(operandType);
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return success();
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}
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//===----------------------------------------------------------------------===//
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// TableGen'd attribute method definitions
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//===----------------------------------------------------------------------===//

mlir/lib/Target/DXSA/BinaryParser.cpp

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@@ -635,6 +635,12 @@ class DXBuilder {
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return dxsa::DclOutput::create(builder, loc, operand);
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}
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Instruction buildDclIndexRange(dxsa::InlineOperandAttr operand,
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uint32_t count, Location loc) {
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return dxsa::DclIndexRange::create(builder, loc, operand,
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builder.getI32IntegerAttr(count));
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}
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private:
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MLIRContext *context;
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ModuleOp module;
@@ -1174,6 +1180,14 @@ class Parser {
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return builder.buildDclOutput(*operand, loc);
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}
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FailureOr<Instruction> parseDclIndexRange(Location loc) {
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auto operand = parseInlineOperand();
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FAILURE_IF_FAILED(operand);
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auto count = parseToken();
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FAILURE_IF_FAILED(count);
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return builder.buildDclIndexRange(*operand, *count, loc);
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}
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OptionalParseResult parseDclInstruction(uint32_t opcodeToken, Location loc,
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Instruction &out) {
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FailureOr<Instruction> result;
@@ -1220,6 +1234,9 @@ class Parser {
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case D3D10_SB_OPCODE_DCL_OUTPUT:
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result = parseDclOutput(loc);
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break;
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case D3D10_SB_OPCODE_DCL_INDEX_RANGE:
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result = parseDclIndexRange(loc);
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break;
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default:
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return std::nullopt;
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}
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@@ -0,0 +1,6 @@
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// RUN: mlir-translate --import-dxsa-bin %S/inputs/dcl_index_range.bin | FileCheck %s
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// CHECK: module {
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// CHECK-NEXT: dxsa.dcl_index_range <type = input, components = 4, mask = <x, y, z, w>, index = [4]>, 6
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// CHECK-NEXT: dxsa.dcl_index_range <type = output, components = 4, mask = <x>, index = [0]>, 4
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// CHECK-NEXT: }
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// RUN: mlir-opt %s -split-input-file -verify-diagnostics
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// expected-error@+1 {{'dxsa.dcl_index_range' op operand must be an input or output register, got temp}}
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dxsa.dcl_index_range <type = temp, components = 4, mask = <x, y, z, w>, index = [0]>, 3
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// -----
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// expected-error@+1 {{attribute 'count' failed to satisfy constraint: 32-bit signless integer attribute whose value is positive}}
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dxsa.dcl_index_range <type = input, components = 4, mask = <x, y, z, w>, index = [0]>, 0
32 Bytes
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