diff --git a/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td b/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td
index ed5a295a38db..8893642cea2b 100644
--- a/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td
+++ b/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td
@@ -719,4 +719,22 @@ def DXSA_DclOutput : DXSA_Op<"dcl_output"> {
   let assemblyFormat = "$operand attr-dict";
 }
 
+def DXSA_DclIndexRange : DXSA_Op<"dcl_index_range"> {
+  let summary = "declares a range of input or output registers to be indexed";
+  let description = [{
+    The `dxsa.dcl_index_range` operation declares a range of input or output
+    registers to be indexed.
+
+    Example:
+
+    ```mlir
+    dxsa.dcl_index_range <type = output, components = 4, mask = <x>, index = [0]>, 4
+    ```
+  }];
+  let arguments = (ins DXSA_InlineOperandAttr:$operand,
+                       ConfinedAttr<I32Attr, [IntPositive]>:$count);
+  let assemblyFormat = "$operand `,` $count attr-dict";
+  let hasVerifier = 1;
+}
+
 #endif // DXSA_OPS
diff --git a/mlir/lib/Dialect/DXSA/IR/DXSA.cpp b/mlir/lib/Dialect/DXSA/IR/DXSA.cpp
index e5c94051e3a5..c34132d9cd82 100644
--- a/mlir/lib/Dialect/DXSA/IR/DXSA.cpp
+++ b/mlir/lib/Dialect/DXSA/IR/DXSA.cpp
@@ -41,6 +41,19 @@ void DXSADialect::initialize() {
 #define GET_OP_CLASSES
 #include "mlir/Dialect/DXSA/IR/DXSAOps.cpp.inc"
 
+//===----------------------------------------------------------------------===//
+// Op verifiers
+//===----------------------------------------------------------------------===//
+
+LogicalResult DclIndexRange::verify() {
+  auto operandType = getOperand().getType();
+  if (operandType != InlineOperandType::input &&
+      operandType != InlineOperandType::output)
+    return emitOpError("operand must be an input or output register, got ")
+           << stringifyInlineOperandType(operandType);
+  return success();
+}
+
 //===----------------------------------------------------------------------===//
 // TableGen'd attribute method definitions
 //===----------------------------------------------------------------------===//
diff --git a/mlir/lib/Target/DXSA/BinaryParser.cpp b/mlir/lib/Target/DXSA/BinaryParser.cpp
index f1c860c758a2..44bf68d2667a 100644
--- a/mlir/lib/Target/DXSA/BinaryParser.cpp
+++ b/mlir/lib/Target/DXSA/BinaryParser.cpp
@@ -635,6 +635,12 @@ class DXBuilder {
     return dxsa::DclOutput::create(builder, loc, operand);
   }
 
+  Instruction buildDclIndexRange(dxsa::InlineOperandAttr operand,
+                                 uint32_t count, Location loc) {
+    return dxsa::DclIndexRange::create(builder, loc, operand,
+                                       builder.getI32IntegerAttr(count));
+  }
+
 private:
   MLIRContext *context;
   ModuleOp module;
@@ -1174,6 +1180,14 @@ class Parser {
     return builder.buildDclOutput(*operand, loc);
   }
 
+  FailureOr<Instruction> parseDclIndexRange(Location loc) {
+    auto operand = parseInlineOperand();
+    FAILURE_IF_FAILED(operand);
+    auto count = parseToken();
+    FAILURE_IF_FAILED(count);
+    return builder.buildDclIndexRange(*operand, *count, loc);
+  }
+
   OptionalParseResult parseDclInstruction(uint32_t opcodeToken, Location loc,
                                           Instruction &out) {
     FailureOr<Instruction> result;
@@ -1220,6 +1234,9 @@ class Parser {
     case D3D10_SB_OPCODE_DCL_OUTPUT:
       result = parseDclOutput(loc);
       break;
+    case D3D10_SB_OPCODE_DCL_INDEX_RANGE:
+      result = parseDclIndexRange(loc);
+      break;
     default:
       return std::nullopt;
     }
diff --git a/mlir/test/Target/DXSA/dcl_index_range.mlir b/mlir/test/Target/DXSA/dcl_index_range.mlir
new file mode 100644
index 000000000000..1f43055a3264
--- /dev/null
+++ b/mlir/test/Target/DXSA/dcl_index_range.mlir
@@ -0,0 +1,6 @@
+// RUN: mlir-translate --import-dxsa-bin %S/inputs/dcl_index_range.bin | FileCheck %s
+
+// CHECK:      module {
+// CHECK-NEXT:   dxsa.dcl_index_range <type = input, components = 4, mask = <x, y, z, w>, index = [4]>, 6
+// CHECK-NEXT:   dxsa.dcl_index_range <type = output, components = 4, mask = <x>, index = [0]>, 4
+// CHECK-NEXT: }
diff --git a/mlir/test/Target/DXSA/dcl_index_range_invalid.mlir b/mlir/test/Target/DXSA/dcl_index_range_invalid.mlir
new file mode 100644
index 000000000000..a9517b70de90
--- /dev/null
+++ b/mlir/test/Target/DXSA/dcl_index_range_invalid.mlir
@@ -0,0 +1,9 @@
+// RUN: mlir-opt %s -split-input-file -verify-diagnostics
+
+// expected-error@+1 {{'dxsa.dcl_index_range' op operand must be an input or output register, got temp}}
+dxsa.dcl_index_range <type = temp, components = 4, mask = <x, y, z, w>, index = [0]>, 3
+
+// -----
+
+// expected-error@+1 {{attribute 'count' failed to satisfy constraint: 32-bit signless integer attribute whose value is positive}}
+dxsa.dcl_index_range <type = input, components = 4, mask = <x, y, z, w>, index = [0]>, 0
diff --git a/mlir/test/Target/DXSA/inputs/dcl_index_range.bin b/mlir/test/Target/DXSA/inputs/dcl_index_range.bin
new file mode 100644
index 000000000000..ac081c4f8d45
Binary files /dev/null and b/mlir/test/Target/DXSA/inputs/dcl_index_range.bin differ