From 0654b0d5b8cd9eb106a450748ff9342b7c304e92 Mon Sep 17 00:00:00 2001 From: Vladimir Shiryaev Date: Sat, 23 May 2026 21:41:34 -0700 Subject: [PATCH] [mlir][dxsa] Add dcl_tgsm_raw instruction Example: dxsa.dcl_tgsm_raw , 40 Signed-off-by: Vladimir Shiryaev --- mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td | 30 ++++++++++++++---- mlir/lib/Dialect/DXSA/IR/DXSA.cpp | 7 ++++ mlir/lib/Target/DXSA/BinaryParser.cpp | 17 ++++++++++ mlir/test/Target/DXSA/dcl_tgsm_raw.mlir | 5 +++ .../Target/DXSA/dcl_tgsm_raw_invalid.mlir | 14 ++++++++ mlir/test/Target/DXSA/inputs/dcl_tgsm_raw.bin | Bin 0 -> 16 bytes 6 files changed, 66 insertions(+), 7 deletions(-) create mode 100644 mlir/test/Target/DXSA/dcl_tgsm_raw.mlir create mode 100644 mlir/test/Target/DXSA/dcl_tgsm_raw_invalid.mlir create mode 100644 mlir/test/Target/DXSA/inputs/dcl_tgsm_raw.bin diff --git a/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td b/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td index b9d455045ff4..c4a86d4dfcdc 100644 --- a/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td +++ b/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td @@ -485,13 +485,7 @@ def DXSA_InlineOperandAttr : AttrDef { "uint32_t":$components, OptionalParameter<"::mlir::dxsa::ComponentMaskAttr">:$mask, OptionalParameter<"::mlir::DenseI64ArrayAttr">:$index); - let assemblyFormat = [{ - `<` `type` `=` $type - `,` `components` `=` $components - (`,` `mask` `=` $mask^)? - (`,` `index` `=` $index^)? - `>` - }]; + let assemblyFormat = "`<` struct(params) `>`"; } def DXSA_DclGlobalFlags : DXSA_Op<"dcl_global_flags"> { @@ -878,4 +872,26 @@ def DXSA_DclMaxOutputVertexCount : let assemblyFormat = [{ $count attr-dict }]; } +def DXSA_DclTgsmRaw : DXSA_Op<"dcl_tgsm_raw"> { + let summary = "declares a reference to a Thread Group Shared Memory region"; + let description = [{ + The `dxsa.dcl_tgsm_raw` operation declares a reference to a Thread Group Shared Memory region. + + The `$operand` is the `g#` register being declared. + The `$byte_count$ is the size of the block of untyped shared memory; + must be a multiple of 4. + + Example: + + ```mlir + dxsa.dcl_tgsm_raw , 1024 + ``` + }]; + let arguments = (ins DXSA_InlineOperandAttr:$operand, + ConfinedAttr]>:$byte_count); + let assemblyFormat = "$operand `,` $byte_count attr-dict"; + let hasVerifier = 1; +} + #endif // DXSA_OPS diff --git a/mlir/lib/Dialect/DXSA/IR/DXSA.cpp b/mlir/lib/Dialect/DXSA/IR/DXSA.cpp index 791fd432df2e..029a94dae411 100644 --- a/mlir/lib/Dialect/DXSA/IR/DXSA.cpp +++ b/mlir/lib/Dialect/DXSA/IR/DXSA.cpp @@ -63,6 +63,13 @@ LogicalResult DclHsMaxTessFactor::verify() { return success(); } +LogicalResult DclTgsmRaw::verify() { + auto byteCount = getByteCount(); + if (byteCount % 4 != 0) + return emitOpError("byte count must be a multiple of 4, got ") << byteCount; + return success(); +} + //===----------------------------------------------------------------------===// // TableGen'd attribute method definitions //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Target/DXSA/BinaryParser.cpp b/mlir/lib/Target/DXSA/BinaryParser.cpp index 1fa5b22414d0..46de34369d1b 100644 --- a/mlir/lib/Target/DXSA/BinaryParser.cpp +++ b/mlir/lib/Target/DXSA/BinaryParser.cpp @@ -678,6 +678,12 @@ class DXBuilder { builder, loc, builder.getUI32IntegerAttr(count)); } + Instruction buildDclTgsmRaw(dxsa::InlineOperandAttr operand, + uint32_t byteCount, Location loc) { + return dxsa::DclTgsmRaw::create(builder, loc, operand, + builder.getI32IntegerAttr(byteCount)); + } + private: MLIRContext *context; ModuleOp module; @@ -1284,6 +1290,14 @@ class Parser { return builder.buildDclHsForkPhaseInstanceCount(*count, loc); } + FailureOr parseDclTgsmRaw(Location loc) { + auto operand = parseInlineOperand(); + FAILURE_IF_FAILED(operand); + auto byteCount = parseToken(); + FAILURE_IF_FAILED(byteCount); + return builder.buildDclTgsmRaw(*operand, *byteCount, loc); + } + OptionalParseResult parseDclInstruction(uint32_t opcodeToken, Location loc, Instruction &out) { FailureOr result; @@ -1354,6 +1368,9 @@ class Parser { case D3D11_SB_OPCODE_DCL_HS_FORK_PHASE_INSTANCE_COUNT: result = parseDclHsForkPhaseInstanceCount(loc); break; + case D3D11_SB_OPCODE_DCL_THREAD_GROUP_SHARED_MEMORY_RAW: + result = parseDclTgsmRaw(loc); + break; default: return std::nullopt; } diff --git a/mlir/test/Target/DXSA/dcl_tgsm_raw.mlir b/mlir/test/Target/DXSA/dcl_tgsm_raw.mlir new file mode 100644 index 000000000000..231622666a1c --- /dev/null +++ b/mlir/test/Target/DXSA/dcl_tgsm_raw.mlir @@ -0,0 +1,5 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/dcl_tgsm_raw.bin | FileCheck %s + +// CHECK: module { +// CHECK-NEXT: dxsa.dcl_tgsm_raw , 40 +// CHECK-NEXT: } diff --git a/mlir/test/Target/DXSA/dcl_tgsm_raw_invalid.mlir b/mlir/test/Target/DXSA/dcl_tgsm_raw_invalid.mlir new file mode 100644 index 000000000000..b3bc437c533a --- /dev/null +++ b/mlir/test/Target/DXSA/dcl_tgsm_raw_invalid.mlir @@ -0,0 +1,14 @@ +// RUN: mlir-opt %s -split-input-file -verify-diagnostics + +// expected-error@+1 {{'dxsa.dcl_tgsm_raw' op byte count must be a multiple of 4, got 42}} +dxsa.dcl_tgsm_raw , 42 + +// ----- + +// expected-error@+1 {{attribute 'byte_count' failed to satisfy constraint: 32-bit signless integer attribute whose value is positive whose maximum value is 32768}} +dxsa.dcl_tgsm_raw , 0 + +// ----- + +// expected-error@+1 {{attribute 'byte_count' failed to satisfy constraint: 32-bit signless integer attribute whose value is positive whose maximum value is 32768}} +dxsa.dcl_tgsm_raw , 32769 diff --git a/mlir/test/Target/DXSA/inputs/dcl_tgsm_raw.bin b/mlir/test/Target/DXSA/inputs/dcl_tgsm_raw.bin new file mode 100644 index 0000000000000000000000000000000000000000..7ab308cf797750ab8632febecac8e906f7d55bb6 GIT binary patch literal 16 TcmbQwz`(-rL689iG=LZY70v<8 literal 0 HcmV?d00001