[mlir][dxsa] Add dadd, ddiv, dmax, dmin, dmul and drcp instructions#190
[mlir][dxsa] Add dadd, ddiv, dmax, dmin, dmul and drcp instructions#190tagolog wants to merge 2 commits into
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| // dxsa.dadd_sat | ||
| //===----------------------------------------------------------------------===// | ||
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| def DXSA_DaddSat : DXSA_BinaryOp<"dadd_sat"> { |
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I'm seeing in the documentation that _sat is an instruction modifier, these aren't actually separate instructions? In that case, would it make sense to find a way to avoid duplicating almost every instruction?
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We decided to support _sat as a separate instruction (s) and a lot of instructions already implemented in this manner.
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That seems inconsistent with the logic @asl gave in #194 against structured MLIR: "This is a bytecode dialect." In the bytecode, these aren't separate opcodes, so if we're modelling the MLIR after what the bytecode looks like, they shouldn't be separate instructions.
If it's decided that we're doing things this way then I'm of course not going to hold up this PR over it; I'm just leaving this comment to make it clear to anyone reading that it's intentional.
Example: dxsa.dadd r<0>, r<1>, r<2> dxsa.ddiv r<0>, r<1>, r<2> dxsa.dmax r<0>, r<1>, r<2> dxsa.dmin r<0>, r<1>, r<2> dxsa.dmul r<0>, r<1>, r<2> dxsa.drcp r<0>, r<1> Signed-off-by: Vladimir Shiryaev <vshiryaev@accesssoftek.com>
…e with --split-input-file Signed-off-by: Vladimir Shiryaev <vshiryaev@accesssoftek.com>
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Example:
dxsa.dadd r<0>, r<1>, r<2>
dxsa.ddiv r<0>, r<1>, r<2>
dxsa.dmax r<0>, r<1>, r<2>
dxsa.dmin r<0>, r<1>, r<2>
dxsa.dmul r<0>, r<1>, r<2>
dxsa.drcp r<0>, r<1>