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[MSP430] Add pattern matching for indirect register addressing
1 parent dc67ba1 commit 3083ec2

3 files changed

Lines changed: 212 additions & 18 deletions

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‎src/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -121,6 +121,7 @@ namespace {
121121
unsigned Opc16);
122122

123123
bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
124+
bool SelectIndirectReg(SDValue N, SDValue &Base);
124125
};
125126
} // end anonymous namespace
126127

@@ -242,6 +243,28 @@ bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
242243
return MatchAddressBase(N, AM);
243244
}
244245

246+
/// SelectIndirectReg - returns true if it is able to match
247+
/// indirect register addressing mode:
248+
/// - RegBase base type
249+
/// - Offset == 0
250+
/// Returns base register by reference.
251+
bool MSP430DAGToDAGISel::SelectIndirectReg(SDValue N, SDValue &Base) {
252+
MSP430ISelAddressMode AM;
253+
if (MatchAddress(N, AM))
254+
return false;
255+
256+
// TODO: does this check filters out SR and PC based addressing modes?
257+
if (AM.BaseType != MSP430ISelAddressMode::RegBase ||
258+
!AM.Base.Reg.getNode())
259+
return false;
260+
261+
if (AM.Disp != 0)
262+
return false;
263+
264+
Base = AM.Base.Reg;
265+
return true;
266+
}
267+
245268
/// SelectAddr - returns true if it is able pattern match an addressing mode.
246269
/// It returns the operands which make up the maximal addressing mode it can
247270
/// match by reference.

‎src/llvm/lib/Target/MSP430/MSP430InstrInfo.td‎

Lines changed: 64 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -154,6 +154,7 @@ def cg16imm : Operand<i16>,
154154
//===----------------------------------------------------------------------===//
155155

156156
def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
157+
def addrIndReg : ComplexPattern<iPTR, 1, "SelectIndirectReg", [], [], 10>;
157158

158159
//===----------------------------------------------------------------------===//
159160
// Pattern Fragments
@@ -288,10 +289,12 @@ let isCall = 1,
288289
def CALLr : II16r<0b101,
289290
(outs), (ins GR16:$rs),
290291
"call\t$rs", [(MSP430call GR16:$rs)]>;
292+
def CALLn : II16n<0b101,
293+
(outs), (ins indreg:$rs),
294+
"call\t$rs", [(MSP430call (load addrIndReg:$rs))]>;
291295
def CALLm : II16m<0b101,
292296
(outs), (ins memsrc:$src),
293297
"call\t$src", [(MSP430call (load addr:$src))]>;
294-
def CALLn : II16n<0b101, (outs), (ins indreg:$rs), "call\t$rs", []>;
295298
def CALLp : II16p<0b101, (outs), (ins postreg:$rs), "call\t$rs", []>;
296299
}
297300

@@ -374,6 +377,10 @@ def MOVZX16rm8 : I8rm<0b0100,
374377
(outs GR16:$rd), (ins memsrc:$src),
375378
"mov.b\t{$src, $rd}",
376379
[(set GR16:$rd, (zextloadi16i8 addr:$src))]>;
380+
def MOVZX16rn8 : I8rn<0b0100,
381+
(outs GR16:$rd), (ins indreg:$rs),
382+
"mov.b\t{$rs, $rd}",
383+
[(set GR16:$rd, (zextloadi16i8 addrIndReg:$rs))]>;
377384
}
378385

379386
let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$rs = $wb" in {
@@ -685,9 +692,14 @@ def RRA16m : II16m<0b010,
685692
"rra\t$src",
686693
[(store (MSP430rra (i16 (load addr:$src))), addr:$src),
687694
(implicit SR)]>;
688-
689-
def RRA8n : II8n<0b010, (outs), (ins indreg:$rs), "rra.b\t$rs", []>;
690-
def RRA16n : II16n<0b010, (outs), (ins indreg:$rs), "rra\t$rs", []>;
695+
def RRA8n : II8n<0b010, (outs), (ins indreg:$rs), "rra.b\t$rs",
696+
[(store
697+
(MSP430rra (i8 (load addrIndReg:$rs))), addrIndReg:$rs),
698+
(implicit SR)]>;
699+
def RRA16n : II16n<0b010, (outs), (ins indreg:$rs), "rra\t$rs",
700+
[(store
701+
(MSP430rra (i16 (load addrIndReg:$rs))), addrIndReg:$rs),
702+
(implicit SR)]>;
691703
def RRA8p : II8p<0b010, (outs), (ins postreg:$rs), "rra.b\t$rs", []>;
692704
def RRA16p : II16p<0b010, (outs), (ins postreg:$rs), "rra\t$rs", []>;
693705

@@ -703,8 +715,18 @@ def RRC16m : II16m<0b000,
703715
[(store (MSP430rrc (i16 (load addr:$src))), addr:$src),
704716
(implicit SR)]>;
705717

706-
def RRC8n : II8n<0b000, (outs), (ins indreg:$rs), "rrc.b\t$rs", []>;
707-
def RRC16n : II16n<0b000, (outs), (ins indreg:$rs), "rrc\t$rs", []>;
718+
def RRC8n : II8n<0b000,
719+
(outs), (ins indreg:$rs),
720+
"rrc.b\t$rs",
721+
[(store
722+
(MSP430rrc (i8 (load addrIndReg:$rs))), addrIndReg:$rs),
723+
(implicit SR)]>;
724+
def RRC16n : II16n<0b000,
725+
(outs), (ins indreg:$rs),
726+
"rrc\t$rs",
727+
[(store
728+
(MSP430rrc (i16 (load addrIndReg:$rs))), addrIndReg:$rs),
729+
(implicit SR)]>;
708730
def RRC8p : II8p<0b000, (outs), (ins postreg:$rs), "rrc.b\t$rs", []>;
709731
def RRC16p : II16p<0b000, (outs), (ins postreg:$rs), "rrc\t$rs", []>;
710732

@@ -716,7 +738,10 @@ def SEXT16m : II16m<0b011,
716738
[(store (sext_inreg (extloadi16i8 addr:$src), i8),
717739
addr:$src),
718740
(implicit SR)]>;
719-
def SEXT16n : II16n<0b011, (outs), (ins indreg:$rs), "sxt\t$rs", []>;
741+
def SEXT16n : II16n<0b011, (outs), (ins indreg:$rs), "sxt\t$rs",
742+
[(store (sext_inreg (extloadi16i8 addrIndReg:$rs), i8),
743+
addrIndReg:$rs),
744+
(implicit SR)]>;
720745
def SEXT16p : II16p<0b011, (outs), (ins postreg:$rs), "sxt\t$rs", []>;
721746

722747
} // Defs = [SR]
@@ -725,7 +750,9 @@ def SWPB16m : II16m<0b001,
725750
(outs), (ins memsrc:$src),
726751
"swpb\t$src",
727752
[(store (bswap (i16 (load addr:$src))), addr:$src)]>;
728-
def SWPB16n : II16n<0b001, (outs), (ins indreg:$rs), "swpb\t$rs", []>;
753+
def SWPB16n : II16n<0b001, (outs), (ins indreg:$rs), "swpb\t$rs",
754+
[(store
755+
(bswap (i16 (load addrIndReg:$rs))), addrIndReg:$rs)]>;
729756
def SWPB16p : II16p<0b001, (outs), (ins postreg:$rs), "swpb\t$rs", []>;
730757

731758
// Integer comparisons
@@ -791,9 +818,15 @@ def CMP16rm : I16rm<0b1001,
791818
(implicit SR)]>;
792819

793820
def CMP8rn : I8rn<0b1001,
794-
(outs), (ins GR8:$rd, indreg:$rs), "cmp.b\t$rs, $rd", []>;
821+
(outs), (ins GR8:$rd, indreg:$rs),
822+
"cmp.b\t$rs, $rd",
823+
[(MSP430cmp GR8:$rd, (load addrIndReg:$rs)),
824+
(implicit SR)]>;
795825
def CMP16rn : I16rn<0b1001,
796-
(outs), (ins GR16:$rd, indreg:$rs), "cmp\t$rs, $rd", []>;
826+
(outs), (ins GR16:$rd, indreg:$rs),
827+
"cmp\t$rs, $rd",
828+
[(MSP430cmp GR16:$rd, (load addrIndReg:$rs)),
829+
(implicit SR)]>;
797830

798831
def CMP8rp : I8rp<0b1001,
799832
(outs), (ins GR8:$rd, postreg:$rs), "cmp.b\t$rs, $rd", []>;
@@ -820,10 +853,16 @@ def CMP16mm : I16mm<0b1001, (outs), (ins memdst:$dst, memsrc:$src),
820853
[(MSP430cmp (load addr:$dst), (i16 (load addr:$src))),
821854
(implicit SR)]>;
822855

823-
def CMP8mn : I8mn<0b1001, (outs), (ins memsrc:$dst, indreg:$rs),
824-
"cmp.b\t$rs, $dst", []>;
825-
def CMP16mn : I16mn<0b1001, (outs), (ins memsrc:$dst, indreg:$rs),
826-
"cmp\t$rs, $dst", []>;
856+
def CMP8mn : I8mn<0b1001,
857+
(outs), (ins memsrc:$dst, indreg:$rs),
858+
"cmp.b\t$rs, $dst",
859+
[(MSP430cmp (load addr:$dst), (i8 (load addrIndReg:$rs))),
860+
(implicit SR)]>;
861+
def CMP16mn : I16mn<0b1001,
862+
(outs), (ins memsrc:$dst, indreg:$rs),
863+
"cmp\t$rs, $dst",
864+
[(MSP430cmp (load addr:$dst), (i16 (load addrIndReg:$rs))),
865+
(implicit SR)]>;
827866

828867
def CMP8mp : I8mp<0b1001, (outs), (ins memsrc:$dst, postreg:$rs),
829868
"cmp.b\t$rs, $dst", []>;
@@ -877,10 +916,16 @@ def BIT16rm : I16rm<0b1011,
877916
[(MSP430cmp (and_su GR16:$rd, (load addr:$src)), 0),
878917
(implicit SR)]>;
879918

880-
def BIT8rn : I8rn<0b1011, (outs), (ins GR8:$rd, indreg:$rs),
881-
"bit.b\t$rs, $rd", []>;
882-
def BIT16rn : I16rn<0b1011, (outs), (ins GR16:$rd, indreg:$rs),
883-
"bit\t$rs, $rd", []>;
919+
def BIT8rn : I8rn<0b1011,
920+
(outs), (ins GR8:$rd, indreg:$rs),
921+
"bit.b\t$rs, $rd",
922+
[(MSP430cmp (and_su GR8:$rd, (load addrIndReg:$rs)), 0),
923+
(implicit SR)]>;
924+
def BIT16rn : I16rn<0b1011,
925+
(outs), (ins GR16:$rd, indreg:$rs),
926+
"bit\t$rs, $rd",
927+
[(MSP430cmp (and_su GR16:$rd, (load addrIndReg:$rs)), 0),
928+
(implicit SR)]>;
884929

885930
def BIT8rp : I8rp<0b1011, (outs), (ins GR8:$rd, postreg:$rs),
886931
"bit.b\t$rs, $rd", []>;
@@ -956,6 +1001,7 @@ def TST16m : InstAlias<"tst\t$dst", (CMP16mc memdst:$dst, 0)>;
9561001

9571002
// extload
9581003
def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1004+
def : Pat<(extloadi16i8 addrIndReg:$rs), (MOVZX16rn8 addrIndReg:$rs)>;
9591005

9601006
// anyext
9611007
def : Pat<(i16 (anyext GR8:$src)),

‎src/llvm/test/CodeGen/MSP430/indreg.ll‎

Lines changed: 125 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,125 @@
1+
; RUN: llc < %s --show-mc-encoding | FileCheck %s
2+
target datalayout = "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16"
3+
target triple = "msp430-elf"
4+
5+
define i16 @bisrn(i16 %x, i16* %a) nounwind {
6+
; CHECK-LABEL: bisrn:
7+
; CHECK: bis @r13, r12
8+
%1 = load i16, i16* %a
9+
%2 = or i16 %1,%x
10+
ret i16 %2
11+
}
12+
define void @bismn(i16* %x, i16* %a) nounwind {
13+
; CHECK-LABEL: bismn:
14+
; CHECK: bis @r13, @r12
15+
%1 = load i16, i16* %x
16+
%2 = load i16, i16* %a
17+
%3 = or i16 %1,%2
18+
store i16 %3, i16* %x, align 2
19+
ret void
20+
}
21+
22+
define i16 @movrn(i16* %g, i16* %i) {
23+
entry:
24+
; CHECK-LABEL: movrn:
25+
; CHECK: mov @r13, r12
26+
%0 = load i16, i16* %i, align 2
27+
ret i16 %0
28+
}
29+
define void @movmn(i16* %g, i16* %i) {
30+
entry:
31+
; CHECK-LABEL: movmn:
32+
; CHECK: mov @r13, @r12
33+
%0 = load i16, i16* %i, align 2
34+
store i16 %0, i16* %g, align 2
35+
ret void
36+
}
37+
38+
define i16 @addrn(i16 %x, i16* %a) nounwind {
39+
; CHECK-LABEL: addrn:
40+
; CHECK: add @r13, r12
41+
%1 = load i16, i16* %a
42+
%2 = add i16 %1,%x
43+
ret i16 %2
44+
}
45+
define void @addmn(i16* %x, i16* %a) nounwind {
46+
; CHECK-LABEL: addmn:
47+
; CHECK: add @r13, @r12
48+
%1 = load i16, i16* %x
49+
%2 = load i16, i16* %a
50+
%3 = add i16 %2, %1
51+
store i16 %3, i16* %x
52+
ret void
53+
}
54+
55+
define i16 @andrn(i16 %x, i16* %a) nounwind {
56+
; CHECK-LABEL: andrn:
57+
; CHECK: and @r13, r12
58+
%1 = load i16, i16* %a
59+
%2 = and i16 %1,%x
60+
ret i16 %2
61+
}
62+
define void @andmn(i16* %x, i16* %a) nounwind {
63+
; CHECK-LABEL: andmn:
64+
; CHECK: and @r13, @r12
65+
%1 = load i16, i16* %x
66+
%2 = load i16, i16* %a
67+
%3 = and i16 %2, %1
68+
store i16 %3, i16* %x
69+
ret void
70+
}
71+
72+
define i16 @xorrn(i16 %x, i16* %a) nounwind {
73+
; CHECK-LABEL: xorrn:
74+
; CHECK: xor @r13, r12
75+
%1 = load i16, i16* %a
76+
%2 = xor i16 %1,%x
77+
ret i16 %2
78+
}
79+
define void @xormn(i16* %x, i16* %a) nounwind {
80+
; CHECK-LABEL: xormn:
81+
; CHECK: xor @r13, @r12
82+
%1 = load i16, i16* %x
83+
%2 = load i16, i16* %a
84+
%3 = xor i16 %2, %1
85+
store i16 %3, i16* %x
86+
ret void
87+
}
88+
89+
define void @cmpmn(i16* %g, i16* %i) {
90+
entry:
91+
; CHECK-LABEL: cmpmn:
92+
; CHECK: cmp @r12, @r13 ; encoding: [0xad,0x9c,0x00,0x00]
93+
%0 = load i16, i16* %g, align 2
94+
%1 = load i16, i16* %i, align 2
95+
%cmp = icmp sgt i16 %0, %1
96+
br i1 %cmp, label %if.then, label %if.end
97+
98+
if.then: ; preds = %entry
99+
store i16 0, i16* %g, align 2
100+
br label %if.end
101+
102+
if.end: ; preds = %if.then, %entry
103+
ret void
104+
}
105+
106+
define void @rra16n(i16* %i) {
107+
entry:
108+
; CHECK-LABEL: rra16n:
109+
; CHECK: rra @r12 ; encoding: [0x2c,0x11]
110+
%0 = load i16, i16* %i, align 2
111+
%shr = ashr i16 %0, 1
112+
store i16 %shr, i16* %i, align 2
113+
ret void
114+
}
115+
116+
define void @sxt16n(i16* %x) {
117+
entry:
118+
; CHECK-LABEL: sxt16n:
119+
; CHECK: sxt @r12 ; encoding: [0xac,0x11]
120+
%0 = bitcast i16* %x to i8*
121+
%1 = load i8, i8* %0, align 1
122+
%conv = sext i8 %1 to i16
123+
store i16 %conv, i16* %x, align 2
124+
ret void
125+
}

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