|
RAM_MODEL[1] = (t.tr_wdata ^ 16'hFFFF); // Write data to register invert. |
This seems like address 0 and 1 both update when we try to write to zero?
Too sleepy to check but it does not seem right. I guess if addr [1] is RO register that updates when addr [0] is written then this makes sense.
but it does not account for when address is 1. Unless uvm_reg handles it? Need to check when fully awake.
uvmBasics/env/src/scoreboard.sv
Line 29 in 0f74ffd
This seems like address 0 and 1 both update when we try to write to zero?
Too sleepy to check but it does not seem right. I guess if addr [1] is RO register that updates when addr [0] is written then this makes sense.
but it does not account for when address is 1. Unless uvm_reg handles it? Need to check when fully awake.