feat: add foundational RISC-V and RVV support infrastructure

[ihb2032]

Motivation & Context

This PR introduces the fundamental infrastructure required to support the RISC-V 64-bit architecture and the RISC-V Vector Extension.

Adding this underlying scaffolding paves the way for significant performance optimizations. Preliminary downstream testing with RVV intrinsics has already demonstrated massive potential, including nearly 9x QPS improvements in int8 workloads without any drop in recall. This PR is the necessary first step to upstream those gains safely and cleanly.

Performance Context:

• Hardware Platform: Muse Pi Pro (16GB RAM + 128GB Storage)
• Dataset: Cohere 1M
• Note: The specific algorithmic optimizations and detailed benchmark reports will be provided in subsequent PRs relying on this foundation.

What's Next?

This is part 1 of a planned series of PRs. Once this foundational PR is merged, follow-up PRs will introduce the actual algorithmic optimizations that utilize these new cpu_features APIs.

Testing Performed

• Successfully compiled and linked natively in a RISC-V environment.
• Verified basic runtime detection and execution stability on the Muse Pi Pro platform.

[greptile-apps]

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