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[#93434] Remove generate blocks and genvars
Signed-off-by: Artur Bieniek <abieniek@antmicro.com>
1 parent 93dcc78 commit 79f7aef

9 files changed

Lines changed: 33 additions & 9 deletions

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source/BodyRemover.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,16 @@ class BodyRemover : public OneTimeRewriter<BodyRemover> {
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removeChildList(node, node.items);
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return VISIT_CHILDREN;
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}
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ShouldVisitChildren handle(const GenerateBlockSyntax& node, bool isNodeRemovable) {
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removeNode(node, isNodeRemovable);
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return VISIT_CHILDREN;
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}
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ShouldVisitChildren handle(const GenerateRegionSyntax& node, bool isNodeRemovable) {
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removeNode(node, isNodeRemovable);
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return VISIT_CHILDREN;
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}
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};
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template bool rewriteLoop<BodyRemover>(std::shared_ptr<SyntaxTree>& tree,

source/MemberRemover.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,11 @@ class MemberRemover : public OneTimeRewriter<MemberRemover> {
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return VISIT_CHILDREN;
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}
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ShouldVisitChildren handle(const GenvarDeclarationSyntax& node, bool isNodeRemovable) {
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removeNode(node, isNodeRemovable);
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return DONT_VISIT_CHILDREN;
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}
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ShouldVisitChildren handle(const StructUnionMemberSyntax& node, bool isNodeRemovable) {
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removeNode(node, isNodeRemovable);
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return DONT_VISIT_CHILDREN;

tests/Makefile

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ test_dont_abort_after_err:
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test: test_short test_caliptra test_comment_dir test_tricky_missing_newline test_irremovable_verilator_config test_comment_dir2
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.PHONY: test_short
11-
test_short: test_short_exit0 test_truncator test_short_exit1 test_short_grep test_short_verilator_errmsg test_short_multi_file_verilator_errmsg test_short_multi_file_flag_y_verilator_errmsg test_short_multi_file_flag_f_verilator_errmsg
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test_short: test_short_exit0 test_truncator test_short_exit1 test_short_grep test_short_verilator_errmsg test_short_multi_file_verilator_errmsg test_short_multi_file_flag_y_verilator_errmsg test_short_multi_file_flag_f_verilator_errmsg test_generate
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.PHONY: test_short_exit0
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test_short_exit0:
@@ -47,6 +47,10 @@ test_short_multi_file_flag_f_verilator_errmsg:
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test_short_exit1:
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@./run_test short_exit1 checkexit1.sh ${INPUT_DIR}/short_in.sv
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.PHONY: test_generate
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test_generate:
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@./run_test generate checkverilator_run_finish.sh ${INPUT_DIR}/generate.sv
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.PHONY: test_short_grep
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test_short_grep:
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@./run_test short_grep checkgrep.sh ${INPUT_DIR}/short_in.sv
Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
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module t;
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initial begin
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$finish;
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end
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endmodule

tests/golden/short_multifile_flag_f_verilator_errmsg/sv-bugpoint-combined.sv

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,6 @@ typedef struct {
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} struct_foo;
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module serial_adder #() ();
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wire [32:0] m;
6-
generate
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endgenerate
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struct_foo foo = '{5,m};
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assign foo.c = 0;
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endmodule

tests/golden/short_multifile_flag_y_verilator_errmsg/sv-bugpoint-combined.sv

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,6 @@ typedef struct {
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} struct_foo;
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module serial_adder #() ();
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wire [32:0] m;
6-
generate
7-
endgenerate
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struct_foo foo = '{5,m};
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assign foo.c = 0;
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endmodule

tests/golden/short_multifile_verilator_errmsg/sv-bugpoint-combined.sv

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Original file line numberDiff line numberDiff line change
@@ -3,8 +3,6 @@ typedef struct {
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} struct_foo;
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module serial_adder #() ();
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wire [32:0] m;
6-
generate
7-
endgenerate
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struct_foo foo = '{5,m};
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assign foo.c = 0;
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endmodule

tests/golden/short_verilator_errmsg/sv-bugpoint-combined.sv

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Original file line numberDiff line numberDiff line change
@@ -3,8 +3,6 @@ typedef struct {
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} struct_foo;
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module serial_adder #() ();
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wire [32:0] m;
6-
generate
7-
endgenerate
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struct_foo foo = '{5,m};
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assign foo.c = 0;
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endmodule

tests/input_files/generate.sv

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
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module t;
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genvar i;
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generate
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endgenerate
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initial begin
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$finish;
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end
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endmodule

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