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Fix broken `verilator_config removal
"dummy variable trick" introduced in [1]: - Results in syntax error that is not rolled back, causing sv-bugpoint to not minimize anything at all if `verilator_config is present - Relies on not-always-true assumtion that `verilator_config block is recognized by slang as trivia This commit: - goes back to removing `verilator_config as separate step - recognizes `begin_keywords as a way to go back from config mode to systemverilog mode [1]: 533abc2 ("Add support for multi-file designs", 2025-02-26) 9e15f30
1 parent 533abc2 commit 8acccf8

10 files changed

Lines changed: 55 additions & 13 deletions

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source/SvBugpoint.cpp

Lines changed: 30 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -120,19 +120,7 @@ bool SvBugpoint::pass(std::shared_ptr<SyntaxTree>& tree, const std::string& pass
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}
121121

122122
void SvBugpoint::minimize() {
123-
for (size_t i = 0; i < paths.size(); i++) {
124-
currentPathIdx = i;
125-
// Append a dummy variable to the end of the file
126-
// Slang appends unknown directives to the next valid Syntax node, but
127-
// if no such node exists, they are not appended to anything.
128-
// This dummy variable allows to remove this directive as part of the DeclRemover pass.
129-
// Example of such directive is `verilator_config
130-
std::ofstream testFile(getOutput(), std::ios::app);
131-
testFile << "int __SV_BUGPOINT_" << currentPathIdx << "_;" << std::endl;
132-
testFile << std::flush;
133-
testFile.close();
134-
}
135-
123+
removeVerilatorConfig();
136124
bool anyChange = true;
137125
while (anyChange) {
138126
anyChange = false;
@@ -184,6 +172,35 @@ void SvBugpoint::minimize() {
184172
}
185173
}
186174

175+
void SvBugpoint::removeVerilatorConfig() {
176+
auto info = AttemptStats("-", "verilatorConfigRemover", this);
177+
for (size_t i = 0; i < paths.size(); i++) {
178+
currentPathIdx = i;
179+
std::ifstream inputFile(getOutput());
180+
std::ofstream testFile(getTmpOutput());
181+
std::string line;
182+
bool doSkip = false;
183+
bool skippedSomething = false;
184+
while (std::getline(inputFile, line)) {
185+
if (line == "`verilator_config") {
186+
doSkip = true;
187+
skippedSomething = true;
188+
} else if (doSkip && line.starts_with("`begin_keywords")) {
189+
doSkip = false;
190+
// There is chance that `begin_keywords is meant to do more than
191+
// merely exit configuration block, so we don't skip it.
192+
testFile << line << "\n";
193+
} else if (!doSkip) {
194+
testFile << line << "\n";
195+
}
196+
}
197+
testFile << std::flush;
198+
if (skippedSomething) { // no reason to test if no modification was done
199+
test(info);
200+
}
201+
}
202+
}
203+
187204
void SvBugpoint::initOutDir() {
188205
mkdir(getOutDir());
189206
if (!std::filesystem::is_empty(getOutDir()) && !force.value_or(false)) {

source/SvBugpoint.hpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ class SvBugpoint {
2727
void setCurrentAttemptIdx(int idx) { currentAttemptIdx = idx; }
2828
void dryRun();
2929
void initOutDir();
30+
void removeVerilatorConfig();
3031
void minimize();
3132
bool pass(std::shared_ptr<SyntaxTree>& tree, const std::string& passIdx = "-");
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Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,2 @@
1+
2+

tests/golden/short_exit1/sv-bugpoint-minimized.sv

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,9 @@ typedef struct {
3636
int b;
3737
} struct_foo;
3838

39+
`verilator_config
40+
lint_off -rule UNUSED -file "*/rtl/prim_onehot_check.sv" -match "Signal is not used: 'clk_i'"
41+
`begin_keywords "1800-2012"
3942
module serial_adder #(WIDTH=32) (
4043
input [WIDTH-1:0] a,
4144
input [WIDTH-1:0] b,
@@ -64,3 +67,5 @@ module serial_adder #(WIDTH=32) (
6467

6568
endmodule
6669

70+
`verilator_config
71+
lint_off -rule UNUSED -file "*/rtl/prim_onehot_check.sv" -match "Signal is not used: 'clk_i'"

tests/golden/short_grep/sv-bugpoint-minimized.sv

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,3 +3,4 @@
33
module full_adder3 (
44
input cin);
55
endmodule
6+

tests/golden/short_multifile_flag_f_verilator_errmsg/sv-bugpoint-minimized.sv

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,8 @@
99

1010

1111

12+
13+
1214
typedef struct {
1315
int b;
1416
} struct_foo;
@@ -22,3 +24,4 @@ module serial_adder #() ();
2224
assign foo.c = 0;
2325

2426
endmodule
27+

tests/golden/short_multifile_flag_y_verilator_errmsg/sv-bugpoint-minimized.sv

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,8 @@
99

1010

1111

12+
13+
1214
typedef struct {
1315
int b;
1416
} struct_foo;
@@ -22,3 +24,4 @@ module serial_adder #() ();
2224
assign foo.c = 0;
2325

2426
endmodule
27+

tests/golden/short_multifile_verilator_errmsg/sv-bugpoint-minimized.sv

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,8 @@
99

1010

1111

12+
13+
1214
typedef struct {
1315
int b;
1416
} struct_foo;
@@ -22,3 +24,4 @@ module serial_adder #() ();
2224
assign foo.c = 0;
2325

2426
endmodule
27+

tests/golden/short_verilator_errmsg/sv-bugpoint-minimized.sv

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@ typedef struct {
44
int b;
55
} struct_foo;
66

7+
`begin_keywords "1800-2012"
78
module serial_adder #() ();
89

910
generate
@@ -13,3 +14,4 @@ module serial_adder #() ();
1314
assign foo.c = 0;
1415

1516
endmodule
17+

tests/input_files/short_in.sv

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,9 @@ typedef struct {
3636
int b;
3737
} struct_foo;
3838

39+
`verilator_config
40+
lint_off -rule UNUSED -file "*/rtl/prim_onehot_check.sv" -match "Signal is not used: 'clk_i'"
41+
`begin_keywords "1800-2012"
3942
module serial_adder #(WIDTH=32) (
4043
input [WIDTH-1:0] a,
4144
input [WIDTH-1:0] b,
@@ -64,3 +67,5 @@ module serial_adder #(WIDTH=32) (
6467

6568
endmodule
6669

70+
`verilator_config
71+
lint_off -rule UNUSED -file "*/rtl/prim_onehot_check.sv" -match "Signal is not used: 'clk_i'"

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