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Remove declaration assignments
1 parent 8acccf8 commit bdd1b29

8 files changed

Lines changed: 20 additions & 11 deletions

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source/MemberRemover.cpp

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ class MemberRemover : public OneTimeRewriter<MemberRemover> {
1010

1111
ShouldVisitChildren handle(const NetDeclarationSyntax& node, bool isNodeRemovable) {
1212
removeNode(node, isNodeRemovable);
13-
return DONT_VISIT_CHILDREN;
13+
return VISIT_CHILDREN;
1414
}
1515

1616
ShouldVisitChildren handle(const StructUnionMemberSyntax& node, bool isNodeRemovable) {
@@ -21,6 +21,11 @@ class MemberRemover : public OneTimeRewriter<MemberRemover> {
2121
ShouldVisitChildren handle(const DeclaratorSyntax& node,
2222
bool isNodeRemovable) { // a.o. enum fields
2323
removeNode(node, isNodeRemovable);
24+
return VISIT_CHILDREN;
25+
}
26+
27+
ShouldVisitChildren handle(const EqualsValueClauseSyntax& node, bool isNodeRemovable) {
28+
removeNode(node, isNodeRemovable);
2429
return DONT_VISIT_CHILDREN;
2530
}
2631

tests/golden/short_exit1/sv-bugpoint-minimized.sv

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -49,14 +49,14 @@ module serial_adder #(WIDTH=32) (
4949
wire [WIDTH:0] k;
5050
wire [WIDTH:0] l;
5151
wire [WIDTH:0] c;
52-
wire [WIDTH:0] m;
52+
wire [32:0] m = k + l + c + a + b;
5353
wire [WIDTH:0] n = 4;
5454

5555
generate for (genvar i = 0; i < WIDTH; i++)
5656
full_adder fa(a[i], b[i], c[i], s[i], c[i+1]);
5757
endgenerate
5858

59-
struct_foo foo = '{5,6};
59+
struct_foo foo = '{5,m};
6060
assign foo.a = 25;
6161
assign foo.c = 0;
6262

tests/golden/short_multifile_flag_f_verilator_errmsg/sv-bugpoint-minimized.sv

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,11 +16,12 @@ typedef struct {
1616
} struct_foo;
1717

1818
module serial_adder #() ();
19+
wire [32:0] m;
1920

2021
generate
2122
endgenerate
2223

23-
struct_foo foo = '{5,6};
24+
struct_foo foo = '{5,m};
2425
assign foo.c = 0;
2526

2627
endmodule

tests/golden/short_multifile_flag_y_verilator_errmsg/sv-bugpoint-minimized.sv

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,11 +16,12 @@ typedef struct {
1616
} struct_foo;
1717

1818
module serial_adder #() ();
19+
wire [32:0] m;
1920

2021
generate
2122
endgenerate
2223

23-
struct_foo foo = '{5,6};
24+
struct_foo foo = '{5,m};
2425
assign foo.c = 0;
2526

2627
endmodule

tests/golden/short_multifile_verilator_errmsg/sv-bugpoint-minimized.sv

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,11 +16,12 @@ typedef struct {
1616
} struct_foo;
1717

1818
module serial_adder #() ();
19+
wire [32:0] m;
1920

2021
generate
2122
endgenerate
2223

23-
struct_foo foo = '{5,6};
24+
struct_foo foo = '{5,m};
2425
assign foo.c = 0;
2526

2627
endmodule

tests/golden/short_verilator_errmsg/sv-bugpoint-minimized.sv

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,11 +6,12 @@ typedef struct {
66

77
`begin_keywords "1800-2012"
88
module serial_adder #() ();
9+
wire [32:0] m;
910

1011
generate
1112
endgenerate
1213

13-
struct_foo foo = '{5,6};
14+
struct_foo foo = '{5,m};
1415
assign foo.c = 0;
1516

1617
endmodule

tests/input_files/short_in.sv

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -49,14 +49,14 @@ module serial_adder #(WIDTH=32) (
4949
wire [WIDTH:0] k;
5050
wire [WIDTH:0] l;
5151
wire [WIDTH:0] c;
52-
wire [WIDTH:0] m;
52+
wire [32:0] m = k + l + c + a + b;
5353
wire [WIDTH:0] n = 4;
5454

5555
generate for (genvar i = 0; i < WIDTH; i++)
5656
full_adder fa(a[i], b[i], c[i], s[i], c[i+1]);
5757
endgenerate
5858

59-
struct_foo foo = '{5,6};
59+
struct_foo foo = '{5,m};
6060
assign foo.a = 25;
6161
assign foo.c = 0;
6262

tests/input_files/short_in/4.sv

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,14 +16,14 @@ module serial_adder #(WIDTH=32) (
1616
wire [WIDTH:0] k;
1717
wire [WIDTH:0] l;
1818
wire [WIDTH:0] c;
19-
wire [WIDTH:0] m;
19+
wire [32:0] m = k + l + c + a + b;
2020
wire [WIDTH:0] n = 4;
2121

2222
generate for (genvar i = 0; i < WIDTH; i++)
2323
full_adder fa(a[i], b[i], c[i], s[i], c[i+1]);
2424
endgenerate
2525

26-
struct_foo foo = '{5,6};
26+
struct_foo foo = '{5,m};
2727
assign foo.a = 25;
2828
assign foo.c = 0;
2929

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