feat: Add full RISC-V 64-bit architecture support

[Dayuxiaoshui]

What problem does this PR solve?

Issue Number: N/A

Problem Summary:

brpc currently does not support RISC-V architecture, which is an emerging open-source instruction set architecture gaining significant traction in server and embedded systems. This PR adds complete RISC-V 64-bit support to enable brpc to run natively on RISC-V platforms.

What is changed and the side effects?

Changed:

Core Implementation:

• Add RISC-V specific atomic operations implementation using lr.w/lr.d and sc.w/sc.d instructions in src/butil/atomicops_internals_riscv_gcc.h (new file, 192 lines)
• Implement RISC-V context switching for bthread using callee-saved registers (s0-s11, fs0-fs5) in src/bthread/context.cpp
• Add cpu_relax() implementation using fence.i instruction for RISC-V in src/bthread/processor.h
• Add RISC-V cycle counter support using rdcycle CSR instruction in src/butil/time.h
• Fix const correctness in AtomicInteger128 mutex operations for architectures without native 128-bit atomic support

Build System:

• Add RISC-V architecture detection macros (ARCH_CPU_RISCV_FAMILY, ARCH_CPU_RISCV64, ARCH_CPU_RISCV32) in src/butil/build_config.h
• Add RISC-V compilation flags (-march=rv64gc) in CMake and Makefile for optimal code generation

Testing & Verification:

Tested on Sophgo SG2044 (RISC-V 64-bit) platform with successful results:

Build Verification:

• ✅ Static library: libbrpc.a (410MB) successfully built
• ✅ Tools compiled: 6 executables (472MB total)
  • parallel_http (76MB)
  • protoc-gen-mcpack (19MB)
  • rpc_press (77MB)
  • rpc_replay (76MB)
  • rpc_view (76MB)
  • trackme_server (76MB)
• ✅ Full compilation from 0% to 100% with no errors
• ✅ CMake successfully detected RISC-V architecture and all dependencies
• ✅ Only deprecated warnings present (no functional impact)

Functional Verification:

• ✅ Atomic operations (32-bit and 64-bit CAS, exchange, increment)
• ✅ Memory barriers (fence instructions)
• ✅ Context switching (bthread creation and switching)
• ✅ Clock cycle counting (rdcycle CSR)
• ✅ CPU relaxation (fence.i instruction)

Side effects:

• Performance effects:

  • Positive: Native RISC-V support enables brpc to run efficiently on RISC-V hardware (SG2044 verified)
  • Positive: Optimized atomic operations using RISC-V's load-reserved/store-conditional instructions
  • Positive: Proper fence.i instruction usage improves spin-lock performance on RISC-V
  • Neutral: For non-RISC-V platforms, there is no performance impact (all changes are compile-time conditionals)

• Breaking backward compatibility:

  • No breaking changes: All changes are additive and RISC-V-specific
  • Backward compatible: Existing x86_64, ARM, and LoongArch support remains unchanged
  • Safe fallback: Uses mutex-based fallback for 128-bit atomic operations on RISC-V (consistent with other non-x86_64 architectures)

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Check List:

• Please make sure your changes are compilable. ✅ Verified: Full compilation successful on Sophgo SG2044 (RISC-V 64-bit)
• When providing us with a new feature, it is best to add related tests. ✅ Verified: All core functionalities tested on SG2044 hardware
• Please follow Contributor Covenant Code of Conduct. ✅ Confirmed

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Files Changed: 11 files changed, 316 insertions(+), 3 deletions(-)

Co-authored-by: gong-flying gongxiaofei24@iscas.ac.cn

[yanglimingcn]

👍

[wwbmmm]

LGTM
Very useful feature, thank you for your contribution!

[wasphin]

Is there any RISC-V CI resource?

[Dayuxiaoshui]

@wasphin Currently it has not been added yet. If needed, I can add information about RISC-V CI here.

[wasphin]

@Dayuxiaoshui Thanks for your contribution, and it's a better to have, maybe in the future, for a more stable maintenance.

[chenBright]

LGTM