nimble/phy: Add support for using GRTC of nRF54L15

In latest nrfx versions the support for RTCx for nRF54L15 has been
removed and the GRTC should be used instead.
The GRTC SYSCOUNTER has a resolution of 1us, so then optimal cputime freq
would be equal to 31250Hz to ensure smooth calculations, but since the LL
timing is tuned for 32768Hz, let's simulate the 32768Hz for now.

Author: mkasenberg

nimble/drivers/nrf5x/src/ble_phy.c

@@ -424,6 +424,10 @@ struct nrf_ccm_data g_nrf_ccm_data;
 #endif
 #endif
 
+#ifdef GRTC_AS_RADIO_TIMER
+uint64_t hal_grtc_counter_get(void);
+#endif
+
 static void
 timer0_reset(void)
 {
@@ -725,6 +729,10 @@ ble_phy_tifs_set(uint16_t tifs)
 static int
 ble_phy_set_start_time(uint32_t cputime, uint8_t rem_us, bool tx)
 {
+#ifdef GRTC_AS_RADIO_TIMER
+    uint64_t now_grtc;
+    uint64_t start_us;
+#endif
     uint32_t next_cc;
     uint32_t cur_cc;
     uint32_t cntr;
@@ -795,8 +803,14 @@ ble_phy_set_start_time(uint32_t cputime, uint8_t rem_us, bool tx)
      * need to account for it.
      */
     next_cc = cputime & 0xffffff;
+#ifdef GRTC_AS_RADIO_TIMER
+    cur_cc = ble_phy_grtc_ticks_to_rtc(NRF_GRTC->CC[3].CCL) & 0xffffff;
+    now_grtc = hal_grtc_counter_get();
+    cntr = ble_phy_grtc_ticks_to_rtc(now_grtc) & 0xffffff;
+#else
     cur_cc = NRF_RTC0->CC[0];
     cntr = NRF_RTC0->COUNTER;
+#endif
 
     delta = (cur_cc - cntr) & 0xffffff;
     if ((delta <= 3) && (delta != 0)) {
@@ -820,10 +834,17 @@ ble_phy_set_start_time(uint32_t cputime, uint8_t rem_us, bool tx)
     }
 #endif
 
+#ifdef GRTC_AS_RADIO_TIMER
+    start_us = now_grtc + ble_phy_rtc_ticks_to_grtc(delta);
+    nrf_grtc_sys_counter_cc_set(NRF_GRTC, 3, start_us);
+    NRF_GRTC->EVENTS_COMPARE[3] = 0;
+    nrf_grtc_sys_counter_compare_event_enable(NRF_GRTC, 3);
+#else
     /* Set RTC compare to start TIMER0 */
     NRF_RTC0->EVENTS_COMPARE[0] = 0;
     nrf_rtc_cc_set(NRF_RTC0, 0, next_cc);
     nrf_rtc_event_enable(NRF_RTC0, RTC_EVTENSET_COMPARE0_Msk);
+#endif
 
     /* Enable PPI */
 #if PHY_USE_FEM
@@ -851,6 +872,9 @@ static int
 ble_phy_set_start_now(void)
 {
     os_sr_t sr;
+#ifdef GRTC_AS_RADIO_TIMER
+    uint64_t now_grtc;
+#endif
     uint32_t now;
     uint32_t radio_rem_us;
 #if PHY_USE_FEM_LNA
@@ -888,6 +912,13 @@ ble_phy_set_start_now(void)
     NRF_TIMER0->EVENTS_COMPARE[2] = 0;
 #endif
 
+#ifdef GRTC_AS_RADIO_TIMER
+    now_grtc = hal_grtc_counter_get();
+    nrf_grtc_sys_counter_cc_set(NRF_GRTC, 3, now_grtc + 91);
+    NRF_GRTC->EVENTS_COMPARE[3] = 0;
+    nrf_grtc_sys_counter_compare_event_enable(NRF_GRTC, 3);
+    now = ble_phy_grtc_ticks_to_rtc(now_grtc);
+#else
     /*
      * Set RTC compare to start TIMER0. We need to set it to at least N+2 ticks
      * from current value to guarantee triggering compare event, but let's set
@@ -898,6 +929,7 @@ ble_phy_set_start_now(void)
     NRF_RTC0->EVENTS_COMPARE[0] = 0;
     nrf_rtc_cc_set(NRF_RTC0, 0, (now + 3) & 0xffffff);
     nrf_rtc_event_enable(NRF_RTC0, RTC_EVTENSET_COMPARE0_Msk);
+#endif
 
 #if PHY_USE_FEM_LNA
     phy_fem_enable_lna();
@@ -2467,7 +2499,9 @@ ble_phy_stop_usec_timer(void)
 #ifndef NRF54L_SERIES
     NRF_TIMER0->TASKS_SHUTDOWN = 1;
 #endif
+#ifndef GRTC_AS_RADIO_TIMER
     nrf_rtc_event_disable(NRF_RTC0, RTC_EVTENSET_COMPARE0_Msk);
+#endif
 }
 
 /**

nimble/drivers/nrf5x/src/nrf54l/phy.c

@@ -87,7 +87,12 @@ phy_ppi_init(void)
     NRF_RADIO->PUBLISH_END = DPPI_CH_PUB(RADIO_EVENTS_END);
     NRF_RADIO->PUBLISH_PAYLOAD = DPPI_CH_PUB(RADIO_EVENTS_PAYLOAD_RADIO);
     NRF_RADIO->PUBLISH_BCMATCH = DPPI_CH_PUB(RADIO_EVENTS_BCMATCH);
+#ifdef GRTC_AS_RADIO_TIMER
+    NRF_GRTC->PUBLISH_COMPARE[3] = DPPI_CH_PUB(DPPI20_GRTC_EVENTS_COMPARE_3);
+    PPIB_PERI_RADIO_0(DPPI20_GRTC_EVENTS_COMPARE_3, RTC0_EVENTS_COMPARE_0);
+#else
     NRF_RTC0->PUBLISH_COMPARE[0] = DPPI_CH_PUB(RTC0_EVENTS_COMPARE_0);
+#endif
 
     NRF_TIMER0->PUBLISH_COMPARE[0] = DPPI_CH_PUB(TIMER0_EVENTS_COMPARE_0);
     NRF_TIMER0->PUBLISH_COMPARE[3] = DPPI_CH_PUB(TIMER0_EVENTS_COMPARE_3);

nimble/drivers/nrf5x/src/nrf54l/phy_ppi.h

@@ -48,6 +48,7 @@
 #define DPPI_CH_GPIOTE20_TASKS_CLR_1            3
 #define DPPI_CH_GPIOTE20_TASKS_SET_2            4
 #define DPPI_CH_GPIOTE20_TASKS_CLR_2            5
+#define DPPI_CH_DPPI20_GRTC_EVENTS_COMPARE_3    6
 
 #define DPPI_CH_ENABLE_ALL  (DPPIC_CHEN_CH0_Msk | DPPIC_CHEN_CH1_Msk | \
                              DPPIC_CHEN_CH2_Msk | DPPIC_CHEN_CH3_Msk | \
@@ -71,6 +72,15 @@
 #define PPIB_RADIO_PERI_4(_src, _dst) PPIB_RADIO_PERI(4, _src, _dst)
 #define PPIB_RADIO_PERI_5(_src, _dst) PPIB_RADIO_PERI(5, _src, _dst)
 
+/* Create PPIB links between PERI and RADIO power domain. */
+#define PPIB_PERI_RADIO(_ch, _src, _dst)                  \
+    NRF_PPIB21->SUBSCRIBE_SEND[_ch] = DPPI_CH_SUB(_src);  \
+    NRF_PPIB11->PUBLISH_RECEIVE[_ch] = DPPI_CH_PUB(_dst); \
+    NRF_DPPIC20->CHENSET |= 1 << DPPI_CH_ ## _src;        \
+    NRF_DPPIC10->CHENSET |= 1 << DPPI_CH_ ## _dst;
+
+#define PPIB_PERI_RADIO_0(_src, _dst) PPIB_PERI_RADIO(0, _src, _dst)
+
 /* Create PPIB link from RADIO to MCU power domain. */
 #define PPIB_RADIO_MCU(_ch, _src, _dst)                   \
     NRF_PPIB10->SUBSCRIBE_SEND[_ch] = DPPI_CH_SUB(_src);  \

nimble/drivers/nrf5x/src/phy_priv.h

@@ -114,6 +114,50 @@ int8_t phy_txpower_round(int8_t dbm);
 #define RADIO_INTENSET_ADDRESS_Msk RADIO_INTENSET00_ADDRESS_Msk
 #define RADIO_INTENSET_READY_Msk RADIO_INTENSET00_READY_Msk
 #include "nrf54l/phy_ppi.h"
+
+#define GRTC_AS_RADIO_TIMER
+
+#ifdef GRTC_AS_RADIO_TIMER
+#include <nrf_grtc.h>
+
+static inline uint64_t
+grtc_counter_get(void)
+{
+    uint32_t counterl_val, counterh_val, counterh;
+    uint64_t counter;
+
+    nrf_grtc_sys_counter_active_set(NRF_GRTC, true);
+    do {
+        counterl_val = nrf_grtc_sys_counter_low_get(NRF_GRTC);
+        counterh = nrf_grtc_sys_counter_high_get(NRF_GRTC);
+    } while (counterh & NRF_GRTC_SYSCOUNTERH_BUSY_MASK);
+
+    do {
+        counterl_val = nrf_grtc_sys_counter_low_get(NRF_GRTC);
+        counterh = nrf_grtc_sys_counter_high_get(NRF_GRTC);
+        counterh_val = counterh & NRF_GRTC_SYSCOUNTERH_VALUE_MASK;
+    } while (counterh & NRF_GRTC_SYSCOUNTERH_BUSY_MASK);
+
+    if (counterh & NRF_GRTC_SYSCOUNTERH_OVERFLOW_MASK) {
+        --counterh_val;
+    }
+
+    counter = ((uint64_t)counterh_val << 32) | counterl_val;
+    return counter;
+}
+
+static inline uint64_t
+ble_phy_rtc_ticks_to_grtc(uint32_t ticks)
+{
+    return (uint64_t)ticks << 5;
+}
+
+static inline uint32_t
+ble_phy_grtc_ticks_to_rtc(uint64_t us)
+{
+    return (uint32_t)(us >> 5);
+}
+#endif
 #endif
 
 #endif /* H_PHY_PRIV_ */