Skip to content

Commit 81c7a2b

Browse files
raiden00plraiden00pl
committed
arch/arm/src/stm32: unify quadrature encoder driver into common/stm32
Merge the per-IP (m0_v1, m3m4_v1v2v3) and per-family (f7/h7/l4) quadrature encoder drivers into a single common/stm32/stm32_qencoder.c, generalized for every STM32 family: - RCC clock-enable and reset use the common stm32_tim_clk.h aliases instead of per-chip register blocks. - 16/32-bit timer width is selected via STM32_HAVE_TIM2_32BITS / STM32_HAVE_TIM5_32BITS instead of per-chip-line #ifdefs. - The TIM1/TIM8 update interrupt uses the unified STM32_IRQ_TIM1UP / TIM8UP names (no per-family fallback). - GPIO input-float configuration is F1 vs. every other family. Signed-off-by: raiden00pl <raiden00@railab.me>
1 parent af52953 commit 81c7a2b

17 files changed

Lines changed: 299 additions & 5263 deletions

‎arch/arm/src/common/stm32/CMakeLists.txt‎

Lines changed: 3 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,9 @@ endif()
5050
if(CONFIG_STM32_ONESHOT)
5151
list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c)
5252
endif()
53+
if(CONFIG_SENSORS_QENCODER AND CONFIG_STM32_QE)
54+
list(APPEND SRCS stm32_qencoder.c)
55+
endif()
5356

5457
if(CONFIG_STM32_PULSECOUNT)
5558
list(APPEND SRCS stm32_pulsecount.c)
@@ -92,7 +95,6 @@ if(CONFIG_STM32_COMMON_LEGACY)
9295
list(APPEND SRCS stm32_sdio_m3m4_v1.c)
9396
endif()
9497

95-
9698
if(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1)
9799
list(APPEND SRCS stm32_ccm_m3m4_v1.c)
98100
endif()
@@ -164,7 +166,6 @@ if(CONFIG_STM32_COMMON_LEGACY)
164166
endif()
165167
endif()
166168

167-
168169
if(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1)
169170
if(CONFIG_STM32_I2C_ALT)
170171
list(APPEND SRCS stm32_i2c_m3m4_v1_alt.c)
@@ -291,10 +292,6 @@ if(CONFIG_STM32_COMMON_LEGACY)
291292
list(APPEND SRCS stm32_capture_m3m4_v1_lowerhalf.c)
292293
endif()
293294

294-
if(CONFIG_SENSORS_QENCODER AND CONFIG_STM32_QE)
295-
list(APPEND SRCS stm32_qencoder_m3m4_v1v2v3.c)
296-
endif()
297-
298295
if(CONFIG_STM32_CAN AND CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1)
299296
if(CONFIG_STM32_CAN_CHARDRIVER)
300297
list(APPEND SRCS stm32_can_m3m4_v1.c)
@@ -458,7 +455,6 @@ if(CONFIG_ARCH_CORTEXM0)
458455
list(APPEND SRCS stm32_rng_m0_v1.c)
459456
endif()
460457

461-
462458
if(CONFIG_STM32_IWDG AND CONFIG_STM32_HAVE_IP_WDG_M0_V1)
463459
list(APPEND SRCS stm32_iwdg_m0_v1.c)
464460
endif()
@@ -476,9 +472,6 @@ if(CONFIG_ARCH_CORTEXM0)
476472
endif()
477473
endif()
478474

479-
if(CONFIG_SENSORS_QENCODER)
480-
list(APPEND SRCS stm32_qencoder_m0_v1.c)
481-
endif()
482475
endif()
483476

484477
if(CONFIG_SENSORS_HALL3PHASE)

‎arch/arm/src/common/stm32/Make.defs‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,9 @@ ifeq ($(CONFIG_STM32_ONESHOT),y)
5656
CHIP_CSRCS += stm32_oneshot.c
5757
CHIP_CSRCS += stm32_oneshot_lowerhalf.c
5858
endif
59+
ifeq ($(CONFIG_SENSORS_QENCODER)$(CONFIG_STM32_QE),yy)
60+
CHIP_CSRCS += stm32_qencoder.c
61+
endif
5962

6063
ifeq ($(CONFIG_STM32_PULSECOUNT),y)
6164
CHIP_CSRCS += stm32_pulsecount.c
@@ -322,9 +325,6 @@ ifeq ($(CONFIG_STM32_CAP),y)
322325
CHIP_CSRCS += stm32_capture_m3m4_v1_lowerhalf.c
323326
endif
324327

325-
ifeq ($(CONFIG_SENSORS_QENCODER)$(CONFIG_STM32_QE),yy)
326-
CHIP_CSRCS += stm32_qencoder_m3m4_v1v2v3.c
327-
endif
328328

329329
ifeq ($(CONFIG_STM32_CAN)$(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1),yy)
330330
ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y)
@@ -526,9 +526,6 @@ endif
526526
endif
527527
endif
528528

529-
ifeq ($(CONFIG_SENSORS_QENCODER),y)
530-
CHIP_CSRCS += stm32_qencoder_m0_v1.c
531-
endif
532529

533530
endif
534531

arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c renamed to arch/arm/src/common/stm32/stm32_qencoder.c

Lines changed: 65 additions & 109 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/****************************************************************************
2-
* arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c
2+
* arch/arm/src/common/stm32/stm32_qencoder.c
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -44,6 +44,7 @@
4444
#include "stm32.h"
4545
#include "stm32_gpio.h"
4646
#include "stm32_tim.h"
47+
#include "stm32_tim_clk.h"
4748
#include "stm32_qencoder.h"
4849

4950
#ifdef CONFIG_SENSORS_QENCODER
@@ -57,49 +58,44 @@
5758
#undef HAVE_32BIT_TIMERS
5859
#undef HAVE_16BIT_TIMERS
5960

60-
/* On the F1 series, all timers are 16-bit. */
61-
62-
#if defined(CONFIG_STM32_STM32F10XX)
63-
64-
# define HAVE_16BIT_TIMERS 1
61+
/* The width in bits of each timer. TIM2 and TIM5 are 32-bit on the families
62+
* that select STM32_HAVE_TIM2_32BITS / STM32_HAVE_TIM5_32BITS; every other
63+
* quadrature-capable timer is 16-bit.
64+
*/
6565

66-
/* The width in bits of each timer */
66+
#define TIM1_BITWIDTH 16
6767

68-
# define TIM1_BITWIDTH 16
68+
#ifdef CONFIG_STM32_HAVE_TIM2_32BITS
69+
# define TIM2_BITWIDTH 32
70+
#else
6971
# define TIM2_BITWIDTH 16
70-
# define TIM3_BITWIDTH 16
71-
# define TIM4_BITWIDTH 16
72-
# define TIM5_BITWIDTH 16
73-
# define TIM8_BITWIDTH 16
74-
75-
/* On the F2, F3, F4 and G4 series, TIM2 and TIM5 are 32-bit.
76-
* All of the rest are 16-bit
77-
*/
72+
#endif
7873

79-
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \
80-
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32G4XXX)
74+
#define TIM3_BITWIDTH 16
75+
#define TIM4_BITWIDTH 16
8176

82-
/* If TIM2 or TIM5 are enabled, then we have 32-bit timers */
77+
#ifdef CONFIG_STM32_HAVE_TIM5_32BITS
78+
# define TIM5_BITWIDTH 32
79+
#else
80+
# define TIM5_BITWIDTH 16
81+
#endif
8382

84-
# if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE)
85-
# define HAVE_32BIT_TIMERS 1
86-
# endif
83+
#define TIM8_BITWIDTH 16
8784

88-
/* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */
85+
/* If an enabled quadrature timer is 32-bit, then we have 32-bit timers */
8986

90-
# if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \
91-
defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE)
92-
# define HAVE_16BIT_TIMERS 1
93-
# endif
87+
#if (defined(CONFIG_STM32_TIM2_QE) && TIM2_BITWIDTH == 32) || \
88+
(defined(CONFIG_STM32_TIM5_QE) && TIM5_BITWIDTH == 32)
89+
# define HAVE_32BIT_TIMERS 1
90+
#endif
9491

95-
/* The width in bits of each timer */
92+
/* If an enabled quadrature timer is 16-bit, then we have 16-bit timers */
9693

97-
# define TIM1_BITWIDTH 16
98-
# define TIM2_BITWIDTH 32
99-
# define TIM3_BITWIDTH 16
100-
# define TIM4_BITWIDTH 16
101-
# define TIM5_BITWIDTH 32
102-
# define TIM8_BITWIDTH 16
94+
#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \
95+
defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) || \
96+
(defined(CONFIG_STM32_TIM2_QE) && TIM2_BITWIDTH == 16) || \
97+
(defined(CONFIG_STM32_TIM5_QE) && TIM5_BITWIDTH == 16)
98+
# define HAVE_16BIT_TIMERS 1
10399
#endif
104100

105101
/* Do we need to support mixed 16- and 32-bit timers */
@@ -172,85 +168,45 @@
172168
#if defined(CONFIG_STM32_STM32F10XX)
173169
# define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_CNF_INFLOAT | \
174170
GPIO_MODE_INPUT)
175-
#elif defined(CONFIG_STM32_STM32F20XX) || \
176-
defined(CONFIG_STM32_STM32F30XX) || \
177-
defined(CONFIG_STM32_STM32F4XXX) || \
178-
defined(CONFIG_STM32_STM32G4XXX)
179-
# define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT)
180171
#else
181-
# error "Unrecognized STM32 chip"
172+
# define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT)
182173
#endif
183174

184-
/* RCC definitions */
185-
186-
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \
187-
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F4XXX)
188-
189-
# define TIMRCCEN_TIM1 STM32_RCC_APB2ENR
190-
# define TIMEN_TIM1 RCC_APB2ENR_TIM1EN
191-
# define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR
192-
# define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST
193-
194-
# define TIMRCCEN_TIM2 STM32_RCC_APB1ENR
195-
# define TIMEN_TIM2 RCC_APB1ENR_TIM2EN
196-
# define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR
197-
# define TIMRST_TIM2 RCC_APB1RSTR_TIM2RST
198-
199-
# define TIMRCCEN_TIM3 STM32_RCC_APB1ENR
200-
# define TIMEN_TIM3 RCC_APB1ENR_TIM3EN
201-
# define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR
202-
# define TIMRST_TIM3 RCC_APB1RSTR_TIM3RST
203-
204-
# define TIMRCCEN_TIM4 STM32_RCC_APB1ENR
205-
# define TIMEN_TIM4 RCC_APB1ENR_TIM4EN
206-
# define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR
207-
# define TIMRST_TIM4 RCC_APB1RSTR_TIM4RST
208-
209-
# define TIMRCCEN_TIM5 STM32_RCC_APB1ENR
210-
# define TIMEN_TIM5 RCC_APB1ENR_TIM5EN
211-
# define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR
212-
# define TIMRST_TIM5 RCC_APB1RSTR_TIM5RST
213-
214-
# define TIMRCCEN_TIM8 STM32_RCC_APB2ENR
215-
# define TIMEN_TIM8 RCC_APB2ENR_TIM8EN
216-
# define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR
217-
# define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST
218-
219-
#elif defined(CONFIG_STM32_STM32G4XXX)
220-
221-
# define TIMRCCEN_TIM1 STM32_RCC_APB2ENR
222-
# define TIMEN_TIM1 RCC_APB2ENR_TIM1EN
223-
# define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR
224-
# define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST
225-
226-
# define TIMRCCEN_TIM2 STM32_RCC_APB1ENR1
227-
# define TIMEN_TIM2 RCC_APB1ENR1_TIM2EN
228-
# define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR1
229-
# define TIMRST_TIM2 RCC_APB1RSTR1_TIM2RST
230-
231-
# define TIMRCCEN_TIM3 STM32_RCC_APB1ENR1
232-
# define TIMEN_TIM3 RCC_APB1ENR1_TIM3EN
233-
# define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR1
234-
# define TIMRST_TIM3 RCC_APB1RSTR1_TIM3RST
235-
236-
# define TIMRCCEN_TIM4 STM32_RCC_APB1ENR1
237-
# define TIMEN_TIM4 RCC_APB1ENR1_TIM4EN
238-
# define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR1
239-
# define TIMRST_TIM4 RCC_APB1RSTR1_TIM4RST
240-
241-
# define TIMRCCEN_TIM5 STM32_RCC_APB1ENR1
242-
# define TIMEN_TIM5 RCC_APB1ENR1_TIM5EN
243-
# define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR1
244-
# define TIMRST_TIM5 RCC_APB1RSTR1_TIM5RST
245-
246-
# define TIMRCCEN_TIM8 STM32_RCC_APB2ENR
247-
# define TIMEN_TIM8 RCC_APB2ENR_TIM8EN
248-
# define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR
249-
# define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST
175+
/* RCC definitions
176+
*
177+
* The timer RCC clock-enable and reset register/bit are provided per family
178+
* by the common stm32_tim_clk.h aliases.
179+
*/
250180

251-
#else
252-
# error "Unrecognized STM32 chip"
253-
#endif
181+
#define TIMRCCEN_TIM1 STM32_RCC_TIM1_EN_REG
182+
#define TIMEN_TIM1 STM32_RCC_TIM1_EN
183+
#define TIMRCCRST_TIM1 STM32_RCC_TIM1_RST_REG
184+
#define TIMRST_TIM1 STM32_RCC_TIM1_RST
185+
186+
#define TIMRCCEN_TIM2 STM32_RCC_TIM2_EN_REG
187+
#define TIMEN_TIM2 STM32_RCC_TIM2_EN
188+
#define TIMRCCRST_TIM2 STM32_RCC_TIM2_RST_REG
189+
#define TIMRST_TIM2 STM32_RCC_TIM2_RST
190+
191+
#define TIMRCCEN_TIM3 STM32_RCC_TIM3_EN_REG
192+
#define TIMEN_TIM3 STM32_RCC_TIM3_EN
193+
#define TIMRCCRST_TIM3 STM32_RCC_TIM3_RST_REG
194+
#define TIMRST_TIM3 STM32_RCC_TIM3_RST
195+
196+
#define TIMRCCEN_TIM4 STM32_RCC_TIM4_EN_REG
197+
#define TIMEN_TIM4 STM32_RCC_TIM4_EN
198+
#define TIMRCCRST_TIM4 STM32_RCC_TIM4_RST_REG
199+
#define TIMRST_TIM4 STM32_RCC_TIM4_RST
200+
201+
#define TIMRCCEN_TIM5 STM32_RCC_TIM5_EN_REG
202+
#define TIMEN_TIM5 STM32_RCC_TIM5_EN
203+
#define TIMRCCRST_TIM5 STM32_RCC_TIM5_RST_REG
204+
#define TIMRST_TIM5 STM32_RCC_TIM5_RST
205+
206+
#define TIMRCCEN_TIM8 STM32_RCC_TIM8_EN_REG
207+
#define TIMEN_TIM8 STM32_RCC_TIM8_EN
208+
#define TIMRCCRST_TIM8 STM32_RCC_TIM8_RST_REG
209+
#define TIMRST_TIM8 STM32_RCC_TIM8_RST
254210

255211
/* Debug ********************************************************************/
256212

0 commit comments

Comments
 (0)