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drivers/serial: Refactor PL011 to be general-purpose
This commit refactors the PL011 UART driver so that it can be re-used for any number of UART interfaces depending on the board/chip. This commit also hooks the UART interface configuration/selection for PL011 UART interfaces into the same Kconfig used for regular UART interfaces. Now UART interfaces are configured in a standard, extensible way. Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
1 parent 2b8be4a commit dd4996a

52 files changed

Lines changed: 940 additions & 773 deletions

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‎arch/arm/src/cxd32xx/cxd32_serial_pl011.c‎

Lines changed: 2 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ void arm_earlyserialinit(void)
5959
* when they are first opened.
6060
*/
6161

62-
pl011_earlyserialinit();
62+
#error "Not implemented"
6363
}
6464
#endif
6565

@@ -73,36 +73,7 @@ void arm_earlyserialinit(void)
7373

7474
void arm_serialinit(void)
7575
{
76-
pl011_serialinit();
76+
#error "Not implemented"
7777
}
7878

79-
#ifdef CONFIG_UART_PL011_PLATFORMIF
80-
/***************************************************************************
81-
* Name: pl011_platform interface
82-
*
83-
* Description:
84-
* see drivers/serial/serial_pl011.c
85-
* pl011_setup
86-
* pl011_shutdown
87-
*
88-
***************************************************************************/
89-
90-
int pl011_platform_setup(uint32_t base)
91-
{
92-
/* If needed, implement platform specific process such as enabling pl011
93-
* to reduce power consumption.
94-
*/
95-
96-
return 0;
97-
}
98-
99-
int pl011_platform_shutdown(uint32_t base)
100-
{
101-
/* If needed, implement platform specific process such as disabling pl011
102-
* to reduce power consumption.
103-
*/
104-
105-
return 0;
106-
}
107-
#endif /* CONFIG_UART_PL011_PLATFORMIF */
10879
#endif /* USE_SERIALDRIVER */

‎arch/arm/src/fvp-v8r-aarch32/Kconfig‎

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,4 +19,44 @@ endchoice # FVP Chip Selection
1919

2020
endmenu # "FVP Chip Selection"
2121

22+
menu "FVP ARMv8-R Peripheral Selection"
23+
24+
config FVP_ARMV8R_UART0
25+
bool "UART0"
26+
default n
27+
select UART_PL011
28+
select UART0_SERIALDRIVER
29+
select ARCH_HAVE_SERIAL_TERMIOS
30+
---help---
31+
Select to enable support for UART0.
32+
33+
config FVP_ARMV8R_UART1
34+
bool "UART1"
35+
default y
36+
select UART_PL011
37+
select UART1_SERIALDRIVER
38+
select ARCH_HAVE_SERIAL_TERMIOS
39+
---help---
40+
Select to enable support for UART1.
41+
42+
config FVP_ARMV8R_UART2
43+
bool "UART2"
44+
default n
45+
select UART_PL011
46+
select UART2_SERIALDRIVER
47+
select ARCH_HAVE_SERIAL_TERMIOS
48+
---help---
49+
Select to enable support for UART2.
50+
51+
config FVP_ARMV8R_UART3
52+
bool "UART3"
53+
default n
54+
select UART_PL011
55+
select UART3_SERIALDRIVER
56+
select ARCH_HAVE_SERIAL_TERMIOS
57+
---help---
58+
Select to enable support for UART3.
59+
60+
endmenu # FVP ARMv8-R Peripheral Selection
61+
2262
endif # ARCH_CHIP_FVP_ARMV8R_AARCH32

‎arch/arm/src/fvp-v8r-aarch32/fvp_serial.c‎

Lines changed: 202 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -38,12 +38,187 @@
3838

3939
#include "arm_internal.h"
4040

41+
/***************************************************************************
42+
* Pre-processor definitions
43+
***************************************************************************/
44+
45+
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
46+
#define CONSOLE_DEV g_pl011_port0
47+
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
48+
#define CONSOLE_DEV g_pl011_port1
49+
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
50+
#define CONSOLE_DEV g_pl011_port2
51+
#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
52+
#define CONSOLE_DEV g_pl011_port3
53+
#endif
54+
55+
/* QEMU-specific configuration parameters */
56+
57+
#define UART0_BASEADDR (0x9c090000)
58+
#define UART0_CLK_FREQ (24000000)
59+
#define UART0_IRQ (37)
60+
61+
#define UART1_BASEADDR (0x9c0a0000)
62+
#define UART1_CLK_FREQ (24000000)
63+
#define UART1_IRQ (38)
64+
65+
#define UART2_BASEADDR (0x9c0b0000)
66+
#define UART2_CLK_FREQ (24000000)
67+
#define UART2_IRQ (39)
68+
69+
#define UART3_BASEADDR (0x9c0c0000)
70+
#define UART3_CLK_FREQ (24000000)
71+
#define UART3_IRQ (40)
72+
73+
/***************************************************************************
74+
* Private data
75+
***************************************************************************/
76+
77+
#ifdef CONFIG_UART0_SERIALDRIVER
78+
static char g_uart0_rx_buf[CONFIG_UART0_RXBUFSIZE];
79+
static char g_uart0_tx_buf[CONFIG_UART0_TXBUFSIZE];
80+
81+
static struct pl011_uart_port_s g_pl011_port0 =
82+
{
83+
.config =
84+
{
85+
.baseaddr = (void *)UART0_BASEADDR,
86+
.baud_rate = CONFIG_UART0_BAUD,
87+
.irq_num = UART0_IRQ,
88+
.sbsa = false,
89+
.sys_clk_freq = UART0_CLK_FREQ,
90+
},
91+
92+
.uart =
93+
{
94+
.recv =
95+
{
96+
.buffer = g_uart0_rx_buf,
97+
.size = CONFIG_UART0_RXBUFSIZE,
98+
},
99+
.xmit =
100+
{
101+
.buffer = g_uart0_tx_buf,
102+
.size = CONFIG_UART0_TXBUFSIZE,
103+
},
104+
},
105+
};
106+
#endif
107+
108+
#ifdef CONFIG_UART1_SERIALDRIVER
109+
static char g_uart1_rx_buf[CONFIG_UART1_RXBUFSIZE];
110+
static char g_uart1_tx_buf[CONFIG_UART1_TXBUFSIZE];
111+
112+
static struct pl011_uart_port_s g_pl011_port1 =
113+
{
114+
.config =
115+
{
116+
.baseaddr = (void *)UART1_BASEADDR,
117+
.baud_rate = CONFIG_UART1_BAUD,
118+
.irq_num = UART1_IRQ,
119+
.sbsa = false,
120+
.sys_clk_freq = UART1_CLK_FREQ,
121+
},
122+
123+
.uart =
124+
{
125+
.recv =
126+
{
127+
.buffer = g_uart1_rx_buf,
128+
.size = CONFIG_UART1_RXBUFSIZE,
129+
},
130+
.xmit =
131+
{
132+
.buffer = g_uart1_tx_buf,
133+
.size = CONFIG_UART1_TXBUFSIZE,
134+
},
135+
},
136+
};
137+
#endif
138+
139+
#ifdef CONFIG_UART2_SERIALDRIVER
140+
static char g_uart2_rx_buf[CONFIG_UART2_RXBUFSIZE];
141+
static char g_uart2_tx_buf[CONFIG_UART2_TXBUFSIZE];
142+
143+
static struct pl011_uart_port_s g_pl011_port2 =
144+
{
145+
.config =
146+
{
147+
.baseaddr = (void *)UART2_BASEADDR,
148+
.baud_rate = CONFIG_UART2_BAUD,
149+
.irq_num = UART2_IRQ,
150+
.sbsa = false,
151+
.sys_clk_freq = UART2_CLK_FREQ,
152+
},
153+
154+
.uart =
155+
{
156+
.recv =
157+
{
158+
.buffer = g_uart2_rx_buf,
159+
.size = CONFIG_UART2_RXBUFSIZE,
160+
},
161+
.xmit =
162+
{
163+
.buffer = g_uart2_tx_buf,
164+
.size = CONFIG_UART2_TXBUFSIZE,
165+
},
166+
},
167+
};
168+
#endif
169+
170+
#ifdef CONFIG_UART3_SERIALDRIVER
171+
static char g_uart3_rx_buf[CONFIG_UART3_RXBUFSIZE];
172+
static char g_uart3_tx_buf[CONFIG_UART3_TXBUFSIZE];
173+
174+
static struct pl011_uart_port_s g_pl011_port3 =
175+
{
176+
.config =
177+
{
178+
.baseaddr = (void *)UART3_BASEADDR,
179+
.baud_rate = CONFIG_UART3_BAUD,
180+
.irq_num = UART3_IRQ,
181+
.sbsa = false,
182+
.sys_clk_freq = UART3_CLK_FREQ,
183+
},
184+
185+
.uart =
186+
{
187+
.recv =
188+
{
189+
.buffer = g_uart3_rx_buf,
190+
.size = CONFIG_UART3_RXBUFSIZE,
191+
},
192+
.xmit =
193+
{
194+
.buffer = g_uart3_tx_buf,
195+
.size = CONFIG_UART3_TXBUFSIZE,
196+
},
197+
},
198+
};
199+
#endif
200+
41201
#ifdef USE_SERIALDRIVER
42202

43203
/***************************************************************************
44204
* Public Functions
45205
***************************************************************************/
46206

207+
/***************************************************************************
208+
* Name: up_putc
209+
*
210+
* Description:
211+
* Provide priority, low-level access to support OS debug writes
212+
*
213+
***************************************************************************/
214+
215+
#ifdef CONSOLE_DEV
216+
void up_putc(int ch)
217+
{
218+
pl011_putc(&CONSOLE_DEV.uart, ch);
219+
}
220+
#endif
221+
47222
/***************************************************************************
48223
* Name: arm_earlyserialinit
49224
*
@@ -58,8 +233,10 @@ void arm_earlyserialinit(void)
58233
* when they are first opened.
59234
*/
60235

61-
#ifdef CONFIG_UART_PL011
62-
pl011_earlyserialinit();
236+
#ifdef CONSOLE_DEV
237+
pl011_dev_init(&CONSOLE_DEV);
238+
CONSOLE_DEV.uart.isconsole = true;
239+
CONSOLE_DEV.uart.ops->setup(&CONSOLE_DEV.uart); /* Early set up */
63240
#endif
64241
}
65242

@@ -73,8 +250,29 @@ void arm_earlyserialinit(void)
73250

74251
void arm_serialinit(void)
75252
{
76-
#ifdef CONFIG_UART_PL011
77-
pl011_serialinit();
253+
#ifdef CONSOLE_DEV
254+
pl011_dev_init(&CONSOLE_DEV);
255+
uart_register("/dev/console", &CONSOLE_DEV.uart);
256+
#endif
257+
258+
#ifdef CONFIG_UART0_SERIALDRIVER
259+
pl011_dev_init(&g_pl011_port0);
260+
uart_register("/dev/ttyS0", &g_pl011_port0.uart);
261+
#endif
262+
263+
#ifdef CONFIG_UART1_SERIALDRIVER
264+
pl011_dev_init(&g_pl011_port1);
265+
uart_register("/dev/ttyS1", &g_pl011_port1.uart);
266+
#endif
267+
268+
#ifdef CONFIG_UART2_SERIALDRIVER
269+
pl011_dev_init(&g_pl011_port2);
270+
uart_register("/dev/ttyS2", &g_pl011_port2.uart);
271+
#endif
272+
273+
#ifdef CONFIG_UART3_SERIALDRIVER
274+
pl011_dev_init(&g_pl011_port3);
275+
uart_register("/dev/ttyS3", &g_pl011_port3.uart);
78276
#endif
79277
}
80278

‎arch/arm/src/goldfish/goldfish_serial.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ void arm_earlyserialinit(void)
4848
* when they are first opened.
4949
*/
5050

51-
pl011_earlyserialinit();
51+
#error "Not implemented"
5252
}
5353

5454
/***************************************************************************
@@ -61,7 +61,7 @@ void arm_earlyserialinit(void)
6161

6262
void arm_serialinit(void)
6363
{
64-
pl011_serialinit();
64+
#error "Not implemented"
6565
}
6666

6767
#endif /* CONFIG_UART_PL011 */

‎arch/arm/src/qemu/Kconfig‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,5 +49,30 @@ config ARCH_CHIP_QEMU_TRUSTZONE
4949
The default is off. And this config can enable/disable
5050
TrustZone in qemu chip.
5151

52+
#####################################################################
53+
# UART Configuration
54+
#####################################################################
55+
56+
menu "QEMU ARMv7A Peripheral Selection"
57+
58+
config QEMU_UART0
59+
bool "UART0"
60+
default y
61+
select UART_PL011
62+
select UART0_SERIALDRIVER
63+
select ARCH_HAVE_SERIAL_TERMIOS
64+
---help---
65+
Select to enable support for UART0.
66+
67+
config QEMU_UART1
68+
bool "UART1"
69+
default n
70+
select UART_PL011
71+
select UART1_SERIALDRIVER
72+
select ARCH_HAVE_SERIAL_TERMIOS
73+
---help---
74+
Select to enable support for UART1.
75+
76+
endmenu # QEMU ARMv7A Peripheral Selection
5277

5378
endif # ARCH_CHIP_QEMU_ARM

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