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arch/risc-v/rp23xx-rv: Add SMP support for dual Hazard3 #19026

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4 changes: 3 additions & 1 deletion arch/risc-v/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -448,13 +448,15 @@ config ARCH_CHIP_RP23XX_RV
select ARCH_RV_ISA_C
select ARCH_HAVE_RESET
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_MISALIGN_EXCEPTION
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_DEBUG
select RISCV_STRING_FUNCTION
select ONESHOT
select ONESHOT_COUNT
select ONESHOT_FAST_DIVISION
select ALARM_ARCH
select ARCH_HAVE_I2CRESET
select ARCH_BOARD_COMMON
---help---
Raspberry Pi RP23XX architectures (RISC-V dual Hazard3).
Expand Down
3 changes: 3 additions & 0 deletions arch/risc-v/src/rp23xx-rv/Kconfig
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Expand Up @@ -5,6 +5,9 @@

comment "RP23XX Configuration Options"

config ARCH_RV_ISA_VENDOR_EXTENSIONS
default "zba_zbb_zbs_zbkb_zcb_zcmp"

config RP23XX_RV_RP2350B
bool "Use RP2350B variant (QFN-80)"
default n
Expand Down
5 changes: 4 additions & 1 deletion arch/risc-v/src/rp23xx-rv/Make.defs
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Expand Up @@ -22,6 +22,10 @@

include common/Make.defs

ifeq ($(CONFIG_SMP),y)
CMN_CSRCS := $(filter-out riscv_smpcall.c riscv_cpustart.c, $(CMN_CSRCS))
endif

# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
HEAD_ASRC = rp23xx_head.S
Expand All @@ -44,7 +48,6 @@ CHIP_CSRCS += rp23xx_pll.c
ifeq ($(CONFIG_SMP),y)
CHIP_CSRCS += rp23xx_cpustart.c
CHIP_CSRCS += rp23xx_smpcall.c
CHIP_CSRCS += rp23xx_cpuidlestack.c
endif

ifeq ($(CONFIG_RP23XX_RV_DMAC),y)
Expand Down
12 changes: 12 additions & 0 deletions arch/risc-v/src/rp23xx-rv/chip.h
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Expand Up @@ -37,11 +37,23 @@

#include <arch/rp23xx-rv/chip.h>

#include "riscv_internal.h"

/****************************************************************************
* Macro Definitions
****************************************************************************/

#ifdef __ASSEMBLY__

#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
.macro setintstack tmp0, tmp1
up_cpu_index \tmp0
li \tmp1, STACKFRAME_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK)
mul \tmp1, \tmp0, \tmp1
la \tmp0, g_intstacktop
sub sp, \tmp0, \tmp1
.endm
#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 15 */

#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_SRC_RP23XX_RV_CHIP_H */
4 changes: 3 additions & 1 deletion arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hazard3.h
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Expand Up @@ -27,11 +27,13 @@
* Included Files
****************************************************************************/

#include "hardware/rp23xx_memorymap.h"
#include "rp23xx_memorymap.h"

/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define hazard3_block() __asm__ volatile ("slt x0, x0, x0" ::: "memory")
#define hazard3_unblock() __asm__ volatile ("slt x0, x0, x1" ::: "memory")

#define hazard3_irqarray_read(csr, index) (READ_AND_SET_CSR(csr, (index)) >> 16)
#define hazard3_irqarray_write(csr, index, data) (WRITE_CSR(csr, (index) | ((uint32_t)(data) << 16)))
Expand Down
2 changes: 0 additions & 2 deletions arch/risc-v/src/rp23xx-rv/hardware/rp23xx_memorymap.h
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Expand Up @@ -26,8 +26,6 @@
* Included Files
****************************************************************************/

#include "hardware/rp23xx_memorymap.h"

/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
Expand Down
2 changes: 1 addition & 1 deletion arch/risc-v/src/rp23xx-rv/hardware/rp23xx_psm.h
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Expand Up @@ -27,7 +27,7 @@
* Included Files
****************************************************************************/

#include "hardware/rp23xx_memorymap.h"
#include "rp23xx_memorymap.h"

/****************************************************************************
* Pre-processor Definitions
Expand Down
2 changes: 1 addition & 1 deletion arch/risc-v/src/rp23xx-rv/hardware/rp23xx_resets.h
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Expand Up @@ -27,7 +27,7 @@
* Included Files
****************************************************************************/

#include "hardware/rp23xx_memorymap.h"
#include "rp23xx_memorymap.h"

/****************************************************************************
* Pre-processor Definitions
Expand Down
2 changes: 1 addition & 1 deletion arch/risc-v/src/rp23xx-rv/hardware/rp23xx_sio.h
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Expand Up @@ -27,7 +27,7 @@
* Included Files
****************************************************************************/

#include "hardware/rp23xx_memorymap.h"
#include "rp23xx_memorymap.h"

/****************************************************************************
* Pre-processor Definitions
Expand Down
2 changes: 1 addition & 1 deletion arch/risc-v/src/rp23xx-rv/hardware/rp23xx_usbctrl_dpsram.h
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Expand Up @@ -27,7 +27,7 @@
* Included Files
****************************************************************************/

#include "hardware/rp23xx_memorymap.h"
#include "rp23xx_memorymap.h"

/****************************************************************************
* Pre-processor Definitions
Expand Down
2 changes: 1 addition & 1 deletion arch/risc-v/src/rp23xx-rv/hardware/rp23xx_usbctrl_regs.h
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Expand Up @@ -27,7 +27,7 @@
* Included Files
****************************************************************************/

#include "hardware/rp23xx_memorymap.h"
#include "rp23xx_memorymap.h"

/****************************************************************************
* Pre-processor Definitions
Expand Down
93 changes: 0 additions & 93 deletions arch/risc-v/src/rp23xx-rv/rp23xx_cpuidlestack.c
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This file was deleted.

59 changes: 26 additions & 33 deletions arch/risc-v/src/rp23xx-rv/rp23xx_cpustart.c
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Expand Up @@ -26,21 +26,15 @@

#include <nuttx/config.h>

#include <stdint.h>
#include <assert.h>
#include <nuttx/debug.h>
#include <string.h>
#include <stdio.h>
#include <errno.h>

#include <nuttx/arch.h>
#include <nuttx/init.h>
#include <nuttx/sched_note.h>

#include "nvic.h"
#include "sched/sched.h"
#include "init/init.h"
#include "riscv_internal.h"
#include "hardware/rp23xx_memorymap.h"
#include "hardware/rp23xx_hazard3.h"
#include "hardware/rp23xx_sio.h"
#include "hardware/rp23xx_psm.h"

Expand All @@ -62,14 +56,14 @@
# define showprogress(c)
#endif

#define CORE1_BOOT_MSG_LEN 6

/****************************************************************************
* Public Data
****************************************************************************/

static volatile bool g_core1_boot;

extern int rp23xx_smp_call_handler(int irq, void *c, void *arg);

/****************************************************************************
* Private Functions
****************************************************************************/
Expand All @@ -90,7 +84,7 @@ static void fifo_drain(void)
getreg32(RP23XX_SIO_FIFO_RD);
}

__asm__ volatile ("sev");
hazard3_unblock();
}

/****************************************************************************
Expand All @@ -114,14 +108,14 @@ static int fifo_comm(uint32_t msg)
while (!(getreg32(RP23XX_SIO_FIFO_ST) & RP23XX_SIO_FIFO_ST_RDY))
;
putreg32(msg, RP23XX_SIO_FIFO_WR);
__asm__ volatile ("sev");
hazard3_unblock();

while (!(getreg32(RP23XX_SIO_FIFO_ST) & RP23XX_SIO_FIFO_ST_VLD))
__asm__ volatile ("wfe");
hazard3_block();

rcv = getreg32(RP23XX_SIO_FIFO_RD);

return msg == rcv;
return (msg == rcv);
}

/****************************************************************************
Expand All @@ -138,25 +132,23 @@ static int fifo_comm(uint32_t msg)

static void core1_boot(void)
{
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Initializes the stack pointer */

riscv_initialize_stack();
#endif

fifo_drain();

/* Setup NVIC */

up_irqinitialize();

/* Per-core timer: enable MTIMER interrupt */

up_timer_initialize();

/* Enable inter-processor FIFO interrupt */

irq_attach(RP23XX_SIO_IRQ_FIFO, rp23xx_smp_call_handler, NULL);
irq_attach(RP23XX_SIO_IRQ_FIFO, riscv_smp_call_handler, NULL);
up_enable_irq(RP23XX_SIO_IRQ_FIFO);

g_core1_boot = true;

UP_DMB();

#ifdef CONFIG_SCHED_INSTRUMENTATION
/* Notify that this CPU has started */

Expand Down Expand Up @@ -203,7 +195,7 @@ int up_cpu_start(int cpu)
{
int i;
struct tcb_s *tcb = current_task(cpu);
uint32_t core1_boot_msg[5];
uint32_t core1_boot_msg[CORE1_BOOT_MSG_LEN];

DPRINTF("cpu=%d\n", cpu);

Expand All @@ -220,35 +212,36 @@ int up_cpu_start(int cpu)
;
clrbits_reg32(RP23XX_PSM_PROC1, RP23XX_PSM_FRCE_OFF);

/* Send initial VTOR, MSP, PC for Core 1 boot */

core1_boot_msg[0] = 0;
core1_boot_msg[1] = 1;
core1_boot_msg[2] = getreg32(NVIC_VECTAB);
core1_boot_msg[3] = (uint32_t)tcb->stack_base_ptr +
core1_boot_msg[1] = 0;
core1_boot_msg[2] = 1;
core1_boot_msg[3] = READ_CSR(CSR_MTVEC);
core1_boot_msg[4] = (uint32_t)tcb->stack_base_ptr +
tcb->adj_stack_size;
core1_boot_msg[4] = (uint32_t)core1_boot;
core1_boot_msg[5] = (uint32_t)core1_boot;

do
{
fifo_drain();
for (i = 0; i < 5; i++)
for (i = 0; i < CORE1_BOOT_MSG_LEN; i++)
{
if (!fifo_comm(core1_boot_msg[i]))
{
break;
}
}
}
while (i < 5);
while (i < CORE1_BOOT_MSG_LEN);

fifo_drain();

/* Enable inter-processor FIFO interrupt */

irq_attach(RP23XX_SIO_IRQ_FIFO, rp23xx_smp_call_handler, NULL);
irq_attach(RP23XX_SIO_IRQ_FIFO, riscv_smp_call_handler, NULL);
up_enable_irq(RP23XX_SIO_IRQ_FIFO);

/* Spin until Core 1 signals that it has finished its initialisation */

while (!g_core1_boot);

/* CPU Core 1 boot done */
Expand Down
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