arch/[risc-v|xtensa]: update Espressif's common source code

[tmedicci]

Summary

• arch/[risc-v|xtensa]: update Espressif's common source code
  • Updates Espressif's common source code to ensure that critical sections are properly handled by the common source code.

Impact

Impact on user: No.

Impact on build: No.

Impact on hardware: No.

Impact on documentation: No.

Impact on security: No.

Impact on compatibility: No.

Testing

The potentially affected devices are ESP32 and ESP32-S3 (the ones that may enable SMP). To test it, simply build the smp defconfig and run the smp and ostest.

Building

For ESP32-S3, for instance:

make -j distclean && ./tools/configure.sh -S esp32s3-devkit:smp && make flash ESPTOOL_PORT=/dev/ttyUSB0 -s -j$(nproc)

Running

With picocom, for instance:

picocom -b 115200 /dev/ttyUSB0

Run smp and ostest on NSH

Results

nsh> smp
  Main[0]: Running on CPU1
  Main[0]: Initializing barrier
  Main[0]: Thread 1 created
Thread[1]: Started
...
Thread[8]: Now running on CPU0
Thread[8]: Done
  Main[0]: Now running on CPU0
  Main[0]: Thread 8 completed with result=0

nsh> ostest
stdio_test: write fd=1
stdio_test: Standard I/O Check: printf
stdio_test: write fd=2
stdio_test: Standard I/O Check: fprintf to stderr
...
user_main: Exiting
ostest_main: Exiting with status 0
nsh> 

[github-actions]

MemBrowse Memory Report

No memory changes detected for:

• arduino-mega2560
• esp32-devkitc
• hifive1-revb
• mirtoo
• qemu-armv8a
• qemu-intel64
• rx65n-rsk2mb
• s698pm-dkit
• stm32-nucleo-f103rb