Support RISC-V 64-bit architecture (riscv64) for AXVisor to boot ArceOS (#66)

* feat: support riscv64 axvisor

* feat: refactor IRQ handling and update memory configurations for RISC-V platform

Author: Josen-B

Cargo.toml

@@ -71,6 +71,7 @@ axstd = { version = "=0.3.0-preview.3", features = [
   "smp",
   "hv",
 ]}
+axhal = { version = "=0.3.0-preview.3", features = ["paging", "irq", "smp", "hv"] }
 
 # System dependent modules provided by ArceOS-Hypervisor (bare-metal only)
 axaddrspace = "0.3.0"
@@ -122,7 +123,9 @@ aarch64-cpu-ext = "0.1"
 arm-gic-driver = {version = "0.17", features = ["rdif"]}
 
 [target.'cfg(target_arch = "riscv64")'.dependencies]
-axplat-riscv64-qemu-virt = "0.3.1-pre.6"
+axplat-riscv64-qemu-virt = { path = "platform/riscv64-qemu-virt" }
+riscv_vcpu = "0.3"
+riscv_vplic = "0.2.2"
 
 # xtask dependencies (only used on host platforms)
 [target.'cfg(any(windows, unix))'.dependencies]

configs/vms/arceos-riscv64-qemu-smp1.toml

@@ -40,7 +40,7 @@ dtb_load_addr = 0x8220_0000
 # Memory regions with format (`base_paddr`, `size`, `flags`, `map_type`).
 # For `map_type`, 0 means `MAP_ALLOC`, 1 means `MAP_IDENTICAL`.
 memory_regions = [
-  [0x8000_0000, 0x800_0000, 0x7, 0], # System RAM 1G MAP_ALLOC
+  [0x8000_0000, 0x400_0000, 0x7, 0], # System RAM 64M MAP_ALLOC
 ]
 
 #

doc/qemu-quickstart.md

@@ -110,6 +110,21 @@ After booting, you will enter the Rust user shell (`>>` prompt). Type `usertests
 
 > **Note**: NimbOS requires VT-x/KVM. If `/dev/kvm` does not exist or has insufficient permissions, you will get a `Permission denied` error. WSL2 requires nested virtualization support in the kernel to use KVM.
 
+### ArceOS (RISC-V64)
+
+```bash
+./scripts/setup_qemu.sh arceos-riscv64
+
+cargo xtask qemu \
+  --build-config configs/board/qemu-riscv64.toml \
+  --qemu-config .github/workflows/qemu-riscv64.toml \
+  --vmconfigs tmp/vmconfigs/arceos-riscv64-qemu-smp1.generated.toml
+```
+
+Success indicator: `Hello, world!` appears in the output.
+
+`qemu-riscv64` currently supports the RISC-V ArceOS guest path. Cross-ISA boot such as `riscv64 AxVisor -> aarch64 ArceOS` is not wired up in the current hypervisor stack.
+
 ## 5. What Does setup_qemu.sh Do?
 
 The script automates three steps, eliminating manual work:

doc/qemu-quickstart_cn.md

@@ -110,6 +110,21 @@ cargo xtask qemu \
 
 > **注意**：NimbOS 依赖 VT-x/KVM。如果 `/dev/kvm` 不存在或权限不足，会报 `Permission denied` 错误。WSL2 需要内核支持嵌套虚拟化才能使用 KVM。
 
+### ArceOS（RISC-V64）
+
+```bash
+./scripts/setup_qemu.sh arceos-riscv64
+
+cargo xtask qemu \
+  --build-config configs/board/qemu-riscv64.toml \
+  --qemu-config .github/workflows/qemu-riscv64.toml \
+  --vmconfigs tmp/vmconfigs/arceos-riscv64-qemu-smp1.generated.toml
+```
+
+启动成功标志：输出中出现 `Hello, world!`
+
+当前 `qemu-riscv64` 这条快速启动链路支持的是 RISC-V 版 ArceOS Guest。像 `riscv64 AxVisor -> aarch64 ArceOS` 这样的跨 ISA 启动，在现有 hypervisor 栈里还没有接通。
+
 ## 5. setup_qemu.sh 做了什么
 
 该脚本自动完成以下三步，省去手动操作：

platform/riscv64-qemu-virt/Cargo.toml

@@ -24,10 +24,10 @@ sbi-rt = { version = "0.0.3", features = ["legacy"] }
 uart_16550 = "0.4.0"
 
 axconfig-macros = "0.2"
-axcpu = { version = "0.3.0-preview.8", features = ["arm-el2"] }
-axplat = "0.3.1-pre.6"
+axcpu = { workspace = true }
+axplat = { workspace = true }
 axvisor_api = "0.3"
-crate_interface = "0.3"
+crate_interface = { workspace = true }
 
 [package.metadata.docs.rs]
 targets = ["riscv64gc-unknown-none-elf"]

platform/riscv64-qemu-virt/axconfig.toml

@@ -9,12 +9,12 @@ package = "axplat-riscv64-qemu-virt"            # str
 # Platform configs
 #
 [plat]
-# Number of CPUs.
-cpu-num = 4                         # uint
+# Maximum number of CPUs.
+max-cpu-num = 4                     # uint
 # Base address of the whole physical memory.
 phys-memory-base = 0x8000_0000      # uint
-# Size of the whole physical memory. (8GB)
-phys-memory-size = 0x1_0000_0000    # uint
+# Size of the whole physical memory. (128M)
+phys-memory-size = 0x800_0000       # uint
 # Base physical address of the kernel image.
 kernel-base-paddr = 0x8020_0000     # uint
 # Base virtual address of the kernel image.
@@ -102,4 +102,4 @@ plic-paddr = 0x0c00_0000            # uint
 #     compatible = "ns16550a";
 # };
 uart-paddr = 0x1000_0000            # uint
-uart-irq = 0x0a                     # uint
+uart-irq = 0x0a                     # uint

platform/riscv64-qemu-virt/src/boot.rs

@@ -7,6 +7,14 @@ static mut BOOT_STACK: [u8; BOOT_STACK_SIZE] = [0; BOOT_STACK_SIZE];
 #[unsafe(link_section = ".data")]
 static mut BOOT_PT_SV39: Aligned4K<[u64; 512]> = Aligned4K::new([0; 512]);
 
+const DTB_HEADER_MAGIC: u32 = 0xd00d_feed;
+const DTB_TOTAL_SIZE_OFFSET: usize = 4;
+const DTB_RELOC_BUF_SIZE: usize = 0x40_000;
+
+#[unsafe(link_section = ".data")]
+static mut DTB_RELOC_BUF: Aligned4K<[u8; DTB_RELOC_BUF_SIZE]> =
+    Aligned4K::new([0; DTB_RELOC_BUF_SIZE]);
+
 #[allow(clippy::identity_op)] // (0x0 << 10) here makes sense because it's an address
 unsafe fn init_boot_page_table() {
     unsafe {
@@ -34,11 +42,41 @@ unsafe fn init_mmu() {
     }
 }
 
+unsafe fn relocate_dtb(dtb_paddr: usize) -> usize {
+    if dtb_paddr == 0 {
+        return 0;
+    }
+
+    let header_ptr = dtb_paddr as *const u8;
+    let magic = unsafe { core::ptr::read_unaligned(header_ptr.cast::<u32>()) };
+    let total_size =
+        unsafe { core::ptr::read_unaligned(header_ptr.add(DTB_TOTAL_SIZE_OFFSET).cast::<u32>()) };
+
+    let magic = u32::from_be(magic);
+    let total_size = u32::from_be(total_size) as usize;
+
+    assert_eq!(magic, DTB_HEADER_MAGIC, "invalid DTB magic: {magic:#x}");
+    assert!(
+        total_size <= DTB_RELOC_BUF_SIZE,
+        "DTB too large: {total_size:#x} > buffer {DTB_RELOC_BUF_SIZE:#x}"
+    );
+
+    unsafe {
+        core::ptr::copy_nonoverlapping(
+            header_ptr,
+            (&raw mut DTB_RELOC_BUF).cast::<u8>(),
+            total_size,
+        );
+    }
+
+    &raw const DTB_RELOC_BUF as usize
+}
+
 /// The earliest entry point for the primary CPU.
 #[unsafe(naked)]
 #[unsafe(no_mangle)]
 #[unsafe(link_section = ".text.boot")]
-unsafe extern "C" fn _start() -> ! {
+unsafe extern fn _start() -> ! {
     // PC = 0x8020_0000
     // a0 = hartid
     // a1 = dtb
@@ -49,6 +87,10 @@ unsafe extern "C" fn _start() -> ! {
         li      t0, {boot_stack_size}
         add     sp, sp, t0              // setup boot stack
 
+        mv      a0, s1
+        call    {relocate_dtb}
+        mv      s1, a0
+
         call    {init_boot_page_table}
         call    {init_mmu}              // setup boot page table and enabel MMU
 
@@ -66,6 +108,7 @@ unsafe extern "C" fn _start() -> ! {
         boot_stack = sym BOOT_STACK,
         init_boot_page_table = sym init_boot_page_table,
         init_mmu = sym init_mmu,
+        relocate_dtb = sym relocate_dtb,
         entry = sym axplat::call_main,
     )
 }

platform/riscv64-qemu-virt/src/lib.rs

@@ -31,7 +31,7 @@ pub mod config {
 }
 
 pub const fn cpu_count() -> usize {
-    config::plat::CPU_NUM
+    config::plat::MAX_CPU_NUM
 }
 
 pub const fn plic_base() -> usize {

platform/riscv64-qemu-virt/src/power.rs

@@ -29,4 +29,9 @@ impl PowerIf for PowerImpl {
             axcpu::asm::halt();
         }
     }
+
+    /// Get the number of CPU cores available on this platform.
+    fn cpu_num() -> usize {
+        crate::config::plat::MAX_CPU_NUM
+    }
 }