update configs for loongarch64 and axstd version

Author: YanLien

.axconfig.toml

@@ -1,9 +1,9 @@
 # Architecture identifier.
-arch = "riscv64" # str
+arch = "loongarch64" # str
 # Platform package.
-package = "axplat-riscv64-qemu-virt" # str
+package = "axplat-loongarch64-qemu-virt" # str
 # Platform identifier.
-platform = "riscv64-qemu-virt" # str
+platform = "loongarch64-qemu-virt" # str
 # Stack size of each task.
 task-stack-size = 0x40000 # uint
 # Number of timer ticks per second (Hz). A timer tick may contain several timer
@@ -15,92 +15,106 @@ ticks-per-sec = 100 # uint
 #
 [devices]
 # IPI interrupt num
-ipi-irq = "0x8000_0000_0000_0001" # uint
+ipi-irq = 12 # uint
+eiointc-irq = 0x03 # uint
+# eiointc@1400 {
+#     reg = <0x00 0x1400 0x00 0x800>;
+#     interrupts = <0x03>;
+#     interrupt-parent = <0x8001>;
+#     #interrupt-cells = <0x01>;
+#     interrupt-controller;
+#     compatible = "loongson,ls2k2000-eiointc";
+#     phandle = <0x8002>;
+# };
+eiointc-paddr = 0x1400 # uint
+# poweroff {
+#     value = <0x00000034>;
+#     offset = <0x00000000>;
+#     compatible = "syscon-poweroff";
+# };
+# ged@100e001c {
+#     reg-io-width = <0x00000001>;
+#     reg-shift = <0x00000000>;
+#     reg = <0x00000000 0x100e001c 0x00000000 0x00000003>;
+#     compatible = "syscon";
+# };
+ged-paddr = 0x100E001C # uint
 # MMIO ranges with format (`base_paddr`, `size`).
 mmio-ranges = [
-    [0x0010_1000, 0x1000],
-    [0x0c00_0000, 0x21_0000],
-    [0x1000_0000, 0x1000],
-    [0x1000_1000, 0x8000],
-    [0x2000_0000, 0x400_0000],
-    [0x3000_0000, 0x1000_0000],
-    [0x4000_0000, 0x4000_0000]
+    [0x1000_0000, 0x0000_0400],
+    [0x100D_0000, 0x0000_1000],
+    [0x100E_0000, 0x0000_1000],
+    [0x1D00_0000, 0x40_0000],
+    [0x1FE0_0000, 0x0000_1000],
+    [0x2000_0000, 0x1000_0000],
+    [0x4000_0000, 0x0002_0000]
 ] # [(uint, uint)]
-# End PCI bus number (`bus-range` property in device tree).
-pci-bus-end = 0xff # uint
+# platic@10000000 {
+#     loongson,pic-base-vec = <0x00>;
+#     interrupt-parent = <0x8002>;
+#     #interrupt-cells = <0x02>;
+#     interrupt-controller;
+#     reg = <0x00 0x10000000 0x00 0x400>;
+#     compatible = "loongson,pch-pic-1.0";
+#     phandle = <0x8003>;
+# };
+pch-pic-paddr = 0x10000000 # uint
+# End PCI bus number.
+pci-bus-end = 0x7f # uint
 # Base physical address of the PCIe ECAM space.
-pci-ecam-base = 0x3000_0000 # uint
-# PCI device memory ranges (`ranges` property in device tree).
+pci-ecam-base = 0x2000_0000 # uint
+# PCI device memory ranges.
 pci-ranges = [
-    [0x0300_0000, 0x1_0000],
-    [0x4000_0000, 0x4000_0000],
-    [0x4_0000_0000, 0x4_0000_0000]
+    [0, 0],
+    [0x4000_0000, 0x0002_0000]
 ] # [(uint, uint)]
-# plic@c000000 {
-#     phandle = <0x03>;
-#     riscv,ndev = <0x5f>;
-#     reg = <0x00 0xc000000 0x00 0x600000>;
-#     interrupts-extended = <0x02 0x0b 0x02 0x09>;
-#     interrupt-controller;
-#     compatible = "sifive,plic-1.0.0\0riscv,plic0";
-# };
-plic-paddr = 0x0c00_0000 # uint
-# rtc@101000 {
-#     interrupts = <0x0b>;
-#     interrupt-parent = <0x03>;
-#     reg = <0x00 0x101000 0x00 0x1000>;
-#     compatible = "google,goldfish-rtc";
-# };
-# RTC (goldfish) Address
-rtc-paddr = 0x10_1000 # uint
+# RTC (ls7a) Address
+rtc-paddr = 0x100d_0100 # uint
 # Timer interrupt frequency in Hz.
-timer-frequency = 10_000_000 # uint
-# Timer interrupt num.
-timer-irq = "0x8000_0000_0000_0005" # uint
-uart-irq = 0x0a # uint
-# serial@10000000 {
-#     interrupts = <0x0a>;
-#     interrupt-parent = <0x03>;
-#     clock-frequency = "\08@";
-#     reg = <0x00 0x10000000 0x00 0x100>;
+timer-frequency = 100_000_000 # uint
+# Timer interrupt number.
+timer-irq = 11 # uint
+uart-irq = 0x2 # uint
+# serial@1fe001e0 {
+#     interrupt-parent = <0x00008003>;
+#     interrupts = <0x00000002 0x00000004>;
+#     clock-frequency = <0x05f5e100>;
+#     reg = <0x00000000 0x1fe001e0 0x00000000 0x00000100>;
 #     compatible = "ns16550a";
 # };
-uart-paddr = 0x1000_0000 # uint
+uart-paddr = 0x1FE001E0 # uint
 # VirtIO MMIO ranges with format (`base_paddr`, `size`).
-virtio-mmio-ranges = [
-    [0x1000_1000, 0x1000],
-    [0x1000_2000, 0x1000],
-    [0x1000_3000, 0x1000],
-    [0x1000_4000, 0x1000],
-    [0x1000_5000, 0x1000],
-    [0x1000_6000, 0x1000],
-    [0x1000_7000, 0x1000],
-    [0x1000_8000, 0x1000]
-] # [(uint, uint)]
+virtio-mmio-ranges = [] # [(uint, uint)]
 
 #
 # Platform configs
 #
 [plat]
 # Stack size on bootstrapping. (256K)
 boot-stack-size = 0x40000 # uint
-# Number of CPUs.
-cpu-num = 1 # uint
+# Maximum number of CPUs.
+max-cpu-num = 1 # uint
+# Base address of the high physical memory.
+high-memory-base = 0x8000_0000 # uint
 # Kernel address space base.
-kernel-aspace-base = "0xffff_ffc0_0000_0000" # uint
+kernel-aspace-base = "0xffff_8000_0000_0000" # uint
 # Kernel address space size.
-kernel-aspace-size = "0x0000_003f_ffff_f000" # uint
+kernel-aspace-size = "0x0000_7fff_ffff_f000" # uint
 # Base physical address of the kernel image.
-kernel-base-paddr = 0x8020_0000 # uint
+kernel-base-paddr = 0x0020_0000 # uint
 # Base virtual address of the kernel image.
-kernel-base-vaddr = "0xffff_ffc0_8020_0000" # uint
+kernel-base-vaddr = "0xffff_8000_0020_0000" # uint
+# Base address of the low physical memory.
+low-memory-base = 0x0 # uint
+# Size of the low physical memory. (256M)
+low-memory-size = 0x1000_0000 # uint
+# Linear mapping offset at boot time.
+phys-boot-offset = "0x9000_0000_0000_0000" # uint
 # Offset of bus address and phys address. some boards, the bus address is
 # different from the physical address.
 phys-bus-offset = 0 # uint
-# Base address of the whole physical memory.
-phys-memory-base = 0x8000_0000 # uint
 # Size of the whole physical memory. (128M)
 phys-memory-size = 0x800_0000 # uint
 # Linear mapping offset, for quick conversions between physical and virtual
 # addresses.
-phys-virt-offset = "0xffff_ffc0_0000_0000" # uint
+phys-virt-offset = "0xffff_8000_0000_0000" # uint