|
13 | 13 |
|
14 | 14 | &usart1 { |
15 | 15 | status = "okay"; |
| 16 | + /* usart1 is not set as deferred-init to catch early boot logs since it is assigned to zephyr,console */ |
16 | 17 | }; |
17 | 18 |
|
18 | 19 | &usart2 { |
19 | 20 | status = "okay"; |
| 21 | + zephyr,deferred-init; |
20 | 22 | pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>; |
21 | 23 | pinctrl-names = "default"; |
22 | 24 | current-speed = <115200>; |
23 | 25 | }; |
24 | 26 |
|
25 | 27 | &uart4 { |
26 | 28 | status = "okay"; |
| 29 | + zephyr,deferred-init; |
27 | 30 | pinctrl-0 = <&uart4_tx_ph13 &uart4_rx_pi9>; |
28 | 31 | pinctrl-names = "default"; |
29 | 32 | current-speed = <115200>; |
30 | 33 | }; |
31 | 34 |
|
32 | 35 | &usart6 { |
33 | 36 | status = "okay"; |
| 37 | + zephyr,deferred-init; |
34 | 38 | }; |
35 | 39 |
|
36 | 40 | &rtc { |
|
42 | 46 |
|
43 | 47 | &i2c4 { |
44 | 48 | status = "okay"; |
| 49 | + zephyr,deferred-init; |
45 | 50 | gc2145: gc2145@3c { |
46 | 51 | compatible = "galaxycore,gc2145"; |
47 | 52 | reg = <0x3c>; |
|
58 | 63 |
|
59 | 64 | &i2c1 { |
60 | 65 | status = "okay"; |
| 66 | + zephyr,deferred-init; |
61 | 67 | pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; |
62 | 68 | pinctrl-names = "default"; |
63 | 69 | clock-frequency = <I2C_BITRATE_FAST>; |
64 | 70 | }; |
65 | 71 |
|
66 | 72 | &i2c2 { |
67 | 73 | status = "okay"; |
| 74 | + zephyr,deferred-init; |
68 | 75 | pinctrl-0 = <&i2c2_scl_ph4 &i2c2_sda_pb11>; |
69 | 76 | pinctrl-names = "default"; |
70 | 77 | clock-frequency = <I2C_BITRATE_FAST>; |
|
76 | 83 |
|
77 | 84 | pwm1: pwm { |
78 | 85 | status = "okay"; |
| 86 | + zephyr,deferred-init; |
79 | 87 | /* Temporarily removed SPI1 pins */ |
80 | 88 | /* pinctrl-0 = <&tim1_ch3_pj9 &tim1_ch1_pk1 &tim1_ch2_pj11>; */ |
81 | 89 | pinctrl-0 = <&tim1_ch3_pj9 &tim1_ch1_pk1>; |
|
89 | 97 |
|
90 | 98 | pwm2: pwm { |
91 | 99 | status = "okay"; |
| 100 | + zephyr,deferred-init; |
92 | 101 | pinctrl-0 = <&tim2_ch4_pa3 &tim2_ch3_pa2>; |
93 | 102 | pinctrl-names = "default"; |
94 | 103 | }; |
|
100 | 109 |
|
101 | 110 | pwm3: pwm { |
102 | 111 | status = "okay"; |
| 112 | + zephyr,deferred-init; |
103 | 113 | pinctrl-0 = <&tim3_ch2_pa7 &tim3_ch1_pb4>; |
104 | 114 | pinctrl-names = "default"; |
105 | 115 | }; |
|
111 | 121 |
|
112 | 122 | pwm4: pwm { |
113 | 123 | status = "okay"; |
| 124 | + zephyr,deferred-init; |
114 | 125 | pinctrl-0 = <&tim4_ch2_pd13 &tim4_ch3_pb8 &tim4_ch4_pb9>; |
115 | 126 | pinctrl-names = "default"; |
116 | 127 | }; |
|
122 | 133 |
|
123 | 134 | pwm8: pwm { |
124 | 135 | status = "okay"; |
| 136 | + zephyr,deferred-init; |
125 | 137 | /* Temporarily removed SPI1 pins */ |
126 | 138 | /* pinctrl-0 = <&tim8_ch1_pj8 &tim8_ch2_pj10>; */ |
127 | 139 | pinctrl-0 = <&tim8_ch1_pj8>; |
|
189 | 201 |
|
190 | 202 | &spi1 { |
191 | 203 | status = "okay"; |
| 204 | + zephyr,deferred-init; |
192 | 205 | pinctrl-0 = <&spi1_sck_pb3 |
193 | 206 | &spi1_miso_pg9 &spi1_mosi_pd7>; |
194 | 207 | pinctrl-names = "default"; |
195 | 208 | }; |
196 | 209 |
|
197 | 210 | &spi5 { |
198 | 211 | status = "okay"; |
| 212 | + zephyr,deferred-init; |
199 | 213 | pinctrl-0 = <&spi5_sck_ph6 |
200 | 214 | &spi5_miso_pj11 &spi5_mosi_pj10>; |
201 | 215 | pinctrl-names = "default"; |
202 | 216 | }; |
203 | 217 |
|
204 | 218 | &adc1 { |
| 219 | + zephyr,deferred-init; |
205 | 220 | pinctrl-0 = <&adc1_inp4_pc4 |
206 | 221 | &adc1_inp8_pc5 |
207 | 222 | &adc1_inp9_pb0 |
|
310 | 325 | }; |
311 | 326 |
|
312 | 327 | &adc3 { |
| 328 | + zephyr,deferred-init; |
313 | 329 | pinctrl-0 = <&adc3_inp0_pc2_c |
314 | 330 | &adc3_inp1_pc3_c>; |
315 | 331 | pinctrl-names = "default"; |
|
336 | 352 | }; |
337 | 353 | }; |
338 | 354 |
|
| 355 | +&dac1 { |
| 356 | + zephyr,deferred-init; |
| 357 | +}; |
| 358 | + |
339 | 359 | /{ |
340 | 360 | chosen { |
341 | 361 | zephyr,camera = &dcmi; |
|
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