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riscv-bench.yml
19 workflow runs
19 workflow runs

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Aiur grammar: statement sequencing t; rest (#475) RISC-V bench #19: Commit e8dbdb4 pushed by arthurpaulino
16m 9s main
main
16m 9s
chore: bump crossbeam-epoch 0.9.18 -> 0.9.20 (RUSTSEC-2026-0204) (#476) RISC-V bench #18: Commit c66b28f pushed by arthurpaulino
20m 58s main
main
20m 58s
Compiler fixes for auxiliary constant generation (#473) RISC-V bench #17: Commit 547455e pushed by johnchandlerburnham
13m 30s main
main
13m 30s
test(ci): trigger bench-main + zkVM-build on branch pushes (TEMPORARY) RISC-V bench #16: Commit 00dd93d pushed by samuelburnham
4m 37s sb/ci-benchmarks
sb/ci-benchmarks
4m 37s
test(ci): trigger bench-main + zkVM-build on branch pushes (TEMPORARY) RISC-V bench #15: Commit c73bafa pushed by samuelburnham
4m 7s sb/ci-benchmarks
sb/ci-benchmarks
4m 7s
IxVM: native execution pipeline (#463) RISC-V bench #14: Commit 77e363b pushed by arthurpaulino
14m 52s main
main
14m 52s
feat(ci): annotate compare table cells with ratio (1.5x faster/slower) RISC-V bench #13: Commit eb6b068 pushed by samuelburnham
12m 20s sb/ci-benchmarks
sb/ci-benchmarks
12m 20s
feat(ci): annotate compare table cells with ratio (1.5x faster/slower) RISC-V bench #12: Commit 43d00a3 pushed by samuelburnham
33s sb/ci-benchmarks
sb/ci-benchmarks
33s
IxVM ingress: blob-ref index, sidecar→rbtree, IOBuffer interface (#457) RISC-V bench #11: Commit 110f28f pushed by arthurpaulino
16m 6s main
main
16m 6s
IxVM kernel: klimbs_pow via binary exponentiation (#455) RISC-V bench #10: Commit 138a736 pushed by arthurpaulino
16m 52s main
main
16m 52s
chore: Test bencher PR comment (#471) RISC-V bench #9: Commit 08e8c51 pushed by samuelburnham
8m 29s main
main
8m 29s
ci: Fix !bencher-thresholds-reset PR comment (#466) RISC-V bench #8: Commit 43564f6 pushed by samuelburnham
14m 0s main
main
14m 0s
ci: Fix bench-thresholds-reset (#462) RISC-V bench #7: Commit 305fa9b pushed by samuelburnham
12m 17s main
main
12m 17s
Fix Zisk ulimit RISC-V bench #6: Commit 4c1315c pushed by samuelburnham
15m 13s ci-fixes
ci-fixes
15m 13s
Fixup RISC-V bench #5: Commit a663147 pushed by samuelburnham
14m 56s ci-fixes
ci-fixes
14m 56s
Temporary test RISC-V bench #4: Commit e94f25a pushed by samuelburnham
14m 30s ci-fixes
ci-fixes
14m 30s
ci: Fix errors (#461) RISC-V bench #3: Commit b7692b3 pushed by samuelburnham
13m 11s main
main
13m 11s
ci: Fix bencher.dev thresholds (#459) RISC-V bench #2: Commit 4b0af6c pushed by samuelburnham
12m 45s main
main
12m 45s
feat: Add SP1 and Zisk kernel proving backends (#411) RISC-V bench #1: Commit c88df18 pushed by samuelburnham
14m 45s main
main
14m 45s