Upgrade Mali DDK to g29p1-12eac0

Documentation/ABI/testing/sysfs-device-mali

@@ -1,21 +1,15 @@
-// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
 /*
  *
- * (C) COPYRIGHT 2017-2024 ARM Limited. All rights reserved.
+ * (C) COPYRIGHT 2023 ARM Limited. All rights reserved.
  *
  * This program is free software and is provided to you under the terms of the
  * GNU General Public License version 2 as published by the Free Software
- * Foundation, and any use by you of this program is subject to the terms
- * of such GNU license.
+ * Foundation) and any use by you of this program is subject to the terms
+ * of such GNU licence.
  *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, you can access it online at
- * http://www.gnu.org/licenses/gpl-2.0.html.
+ * A copy of the licence is included with the program) and can also be obtained
+ * from Free Software Foundation) Inc.) 51 Franklin Street) Fifth Floor)
+ * Boston) MA  02110-1301) USA.
  *
  */
 
@@ -40,6 +34,16 @@ Description:
 		driver, On reading it provides the current DVFS sampling period,
 		on writing a value we set the DVFS sampling period.
 
+What:		/sys/class/misc/mali%u/device/dummy_job_wa_info
+Description:
+		This attribute is available only with platform device that
+                supports a Job Manager based GPU that requires a GPU workaround
+		to execute the dummy fragment job on all shader cores to
+		workaround a hang issue.
+
+		Its a readonly attribute and on reading gives details on the
+		options used with the dummy workaround.
+
 What:		/sys/class/misc/mali%u/device/fw_timeout
 Description:
 		This attribute is available only with mali platform
@@ -74,6 +78,111 @@ Description:
 		is supported or is powered down after suspending command
 		stream groups.
 
+What:		/sys/class/misc/mali%u/device/js_ctx_scheduling_mode
+Description:
+		This attribute is available only with platform device that
+		supports a Job Manager based GPU. This attribute is used to set
+		context scheduling priority for a job slot.
+
+		On Reading it provides the currently set job slot context
+		priority.
+
+		Writing 0 to this attribute sets it to the mode were
+		higher priority atoms will be scheduled first, regardless of
+		the context they belong to. Newly-runnable higher priority atoms
+		can preempt lower priority atoms currently running on the GPU,
+		even if they belong to a different context.
+
+		Writing 1 to this attribute set it to the mode were the
+		highest-priority atom will be chosen from each context in turn
+		using a round-robin algorithm, so priority only has an effect
+		within the context an atom belongs to. Newly-runnable higher
+		priority atoms can preempt the lower priority atoms currently
+		running on the GPU, but only if they belong to the same context.
+
+What:		/sys/class/misc/mali%u/device/js_scheduling_period
+Description:
+		This attribute is available only with platform device that
+                supports a Job Manager based GPU. Used to set the job scheduler
+		tick period in nano-seconds. The Job Scheduler determines the
+		jobs that are run on the GPU, and for how long, Job Scheduler
+		makes decisions at a regular time interval determined by value
+		in js_scheduling_period.
+
+What:		/sys/class/misc/mali%u/device/js_softstop_always
+Description:
+		This attribute is available only with platform device that
+                supports a Job Manager based GPU. Soft-stops are disabled when
+		only a single context is present, this attribute is used to
+		enable soft-stop when only a single context is present can be
+		used for debug and unit-testing purposes.
+
+What:		/sys/class/misc/mali%u/device/js_timeouts
+Description:
+		This attribute is available only with platform device that
+                supports a Job Manager based GPU. It used to set the soft stop
+		and hard stop times for the job scheduler.
+
+		Writing value 0 causes no change, or -1 to restore the
+		default timeout.
+
+		The format used to set js_timeouts is
+		"<soft_stop_ms> <soft_stop_ms_cl> <hard_stop_ms_ss>
+		<hard_stop_ms_cl> <hard_stop_ms_dumping> <reset_ms_ss>
+		<reset_ms_cl> <reset_ms_dumping>"
+
+
+What:		/sys/class/misc/mali%u/device/lp_mem_pool_max_size
+Description:
+		This attribute is used to set the maximum number of large pages
+		memory pools that the driver can contain. Large pages are of
+		size 2MB. On read it displays all the max size of all memory
+		pools and can be used to modify each individual pools as well.
+
+What:		/sys/class/misc/mali%u/device/lp_mem_pool_size
+Description:
+		This attribute is used to set the number of large memory pages
+		which should be	populated, changing this value may cause
+		existing pages to be removed from the pool, or new pages to be
+		created and then added to the pool. On read it will provide
+		pool size for all available pools and we can modify individual
+		pool.
+
+What:		/sys/class/misc/mali%u/device/mem_pool_max_size
+Description:
+		This attribute is used to set the maximum number of small pages
+		for memory pools that the driver can contain. Here small pages
+		are of size 4KB. On read it will display the max size for all
+		available pools and allows us to set max size of
+		individual pools.
+
+What:		/sys/class/misc/mali%u/device/mem_pool_size
+Description:
+		This attribute is used to set the number of small memory pages
+		which should be populated, changing this value may cause
+		existing pages to be removed from the pool, or new pages to
+		be created and then added to the pool. On read it will provide
+		pool size for all available pools and we can modify individual
+		pool.
+
+What:		/sys/class/misc/mali%u/device/device/mempool/ctx_default_max_size
+Description:
+		This attribute is used to set maximum memory pool size for
+		all the memory pool so that the maximum amount of free memory
+		that each pool can hold is identical.
+
+What:		/sys/class/misc/mali%u/device/device/mempool/lp_max_size
+Description:
+		This attribute is used to set the maximum number of large pages
+		for all memory pools that the driver can contain.
+		Large pages are of size 2MB.
+
+What:		/sys/class/misc/mali%u/device/device/mempool/max_size
+Description:
+		This attribute is used to set the maximum number of small pages
+		for all the memory pools that the driver can contain.
+		Here small pages are of size 4KB.
+
 What:		/sys/class/misc/mali%u/device/pm_poweroff
 Description:
 		This attribute contains the current values, represented as the

Documentation/ABI/testing/sysfs-device-mali-coresight-source

@@ -1,21 +1,15 @@
-// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
 /*
  *
- * (C) COPYRIGHT 2017-2024 ARM Limited. All rights reserved.
+ * (C) COPYRIGHT 2023 ARM Limited. All rights reserved.
  *
  * This program is free software and is provided to you under the terms of the
  * GNU General Public License version 2 as published by the Free Software
- * Foundation, and any use by you of this program is subject to the terms
- * of such GNU license.
+ * Foundation) and any use by you of this program is subject to the terms
+ * of such GNU licence.
  *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, you can access it online at
- * http://www.gnu.org/licenses/gpl-2.0.html.
+ * A copy of the licence is included with the program) and can also be obtained
+ * from Free Software Foundation) Inc.) 51 Franklin Street) Fifth Floor)
+ * Boston) MA  02110-1301) USA.
  *
  */
 

Documentation/devicetree/bindings/arm/mali-valhall.txt

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
 #
-# (C) COPYRIGHT 2013-2024 ARM Limited. All rights reserved.
+# (C) COPYRIGHT 2013-2023 ARM Limited. All rights reserved.
 #
 # This program is free software and is provided to you under the terms of the
 # GNU General Public License version 2 as published by the Free Software
@@ -35,14 +35,9 @@ Optional:
 
 - clocks : One or more pairs of phandle to clock and clock specifier
            for the Mali device. The order is important: the first clock
-           shall correspond to the "clk_mali" source. Other clocks are optional
-           and, if present, they shall correspond to domains like "shadercores",
-           which is available for all GPUs, or "coregroup" and "neuralengines"
-           which are available for newer GPUs. Also notice that the "neuralengines"
-           clock domain, if present, doesn't expect a corresponding regulator.
-- clock-names : Shall be set to values like: "clk_mali", "shadercores", "coregroup",
-                "neuralengines". Only the first one is mandatory. Most GPUs
-                support only the first two entries.
+           shall correspond to the "clk_mali" source, while the second clock
+           (that is optional) shall correspond to the "shadercores" source.
+- clock-names : Shall be set to: "clk_mali", "shadercores".
 - mali-supply : Phandle to the top level regulator for the Mali device.
                 Refer to
 Documentation/devicetree/bindings/regulator/regulator.txt for details.
@@ -137,11 +132,6 @@ for details.
 		   set and the setting coresponding to the SYSC_ALLOC register.
 - propagate-bits: Used to write to L2_CONFIG.PBHA_HWU. This bitset establishes which
 		   PBHA bits are propagated on the AXI bus.
-- mma-wa-id: Sets a GPU MMU PBHA value to be used as NONCACHEABLE. GPU Page Table Entries
-	     (PTEs) with this PBHA value set will have uncached transactions from the GPU.
-	     Valid values are from 1 to 15. See mgm_update_gpu_pte() in
-	     include/linux/memory_group_manager.h for the interface to configure the PTEs. Only
-	     supported by arch 14.8.x and later GPUs.
 
 
 Example for a Mali GPU with 1 clock and 1 regulator:
@@ -251,7 +241,6 @@ gpu@0xfc010000 {
     pbha {
         int-id-override = <2 0x32>, <9 0x05>, <16 0x32>;
         propagate-bits = /bits/ 8 <0x03>;
-        mma-wa-id = <2>;
     };
     ...
 };

arch/arm64/boot/dts/rockchip/rk3588s-retroled-cm5.dts

@@ -227,7 +227,7 @@
 
 &usbdp_phy0 {
 	status = "okay";
-	rockchip,dp-lane-mux = <0 1 3 2>;
+	rockchip,dp-lane-mux = <0 1 2 3>;
 };
 
 &dp0 {
@@ -444,12 +444,16 @@
 	rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>;
 	rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER2>;
 	cursor-win-id = <ROCKCHIP_VOP2_ESMART2>;
+	assigned-clocks = <&cru DCLK_VOP3>;
+	assigned-clock-parents = <&cru PLL_V0PLL>;
 };
 
 &vp3 {
 	rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>;
 	rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER3>;
 	cursor-win-id = <ROCKCHIP_VOP2_ESMART3>;
+	assigned-clocks = <&cru DCLK_VOP3>;
+	assigned-clock-parents = <&cru PLL_V0PLL>;
 };
 
 &display_subsystem {
@@ -751,8 +755,3 @@
 	status = "disabled";
 };
 
-&vp3 {
-	assigned-clocks = <&cru DCLK_VOP3>;
-	assigned-clock-parents = <&cru PLL_V0PLL>;
-};
-

drivers/base/arm/Kbuild

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
 #
-# (C) COPYRIGHT 2021-2024 ARM Limited. All rights reserved.
+# (C) COPYRIGHT 2021-2025 ARM Limited. All rights reserved.
 #
 # This program is free software and is provided to you under the terms of the
 # GNU General Public License version 2 as published by the Free Software
@@ -18,14 +18,26 @@
 #
 #
 
-ifeq ($(MALI_CSF_SUPPORT),n)
-    $(error [GPUBUILD-2005] Only CSF builds are supported on this branch)
+# make $(src) as absolute path if it is not already, by prefixing $(srctree) or $(srcroot)
+# depending on Kernel Version (use srctree for < 6.13). This is to prevent any build issue
+# due to wrong path.
+ifeq ($(shell expr $(VERSION) \>= 6), 1)
+    ifeq ($(VERSION), 6)
+        ifeq ($(shell expr $(PATCHLEVEL) \< 13), 1)
+            src:=$(if $(patsubst /%,,$(src)),$(srctree)/$(src),$(src))
+        else
+            src:=$(if $(patsubst /%,,$(src)),$(realpath $(srcroot))/$(src),$(src))
+        endif
+    else
+        src:=$(if $(patsubst /%,,$(src)),$(realpath $(srcroot))/$(src),$(src))
+    endif
+else
+    src:=$(if $(patsubst /%,,$(src)),$(srctree)/$(src),$(src))
 endif
 
 #
 # ccflags
 #
-src:=$(if $(patsubst /%,,$(src)),$(srctree)/$(src),$(src))
 ccflags-y += -I$(src)/../../../include
 
 subdir-ccflags-y += $(ccflags-y)

drivers/base/arm/dma_buf_test_exporter/dma-buf-test-exporter.c

@@ -476,7 +476,7 @@ static int do_dma_buf_te_ioctl_alloc(struct dma_buf_te_ioctl_alloc __user *buf,
 
 	if (copy_from_user(&alloc_req, buf, sizeof(alloc_req))) {
 		dev_err(te_device.this_device, "%s: couldn't get user data", __func__);
-		return -EFAULT;
+		goto no_input;
 	}
 
 	if (!alloc_req.size) {
@@ -604,6 +604,7 @@ static int do_dma_buf_te_ioctl_alloc(struct dma_buf_te_ioctl_alloc __user *buf,
 	kfree(alloc);
 no_alloc_object:
 invalid_size:
+no_input:
 	return -EFAULT;
 }
 

drivers/base/arm/memory_group_manager/memory_group_manager.c

@@ -299,8 +299,7 @@ static int example_mgm_get_import_memory_id(struct memory_group_manager_device *
 }
 
 static u64 example_mgm_update_gpu_pte(struct memory_group_manager_device *const mgm_dev,
-				      unsigned int const group_id, unsigned int const pbha_id,
-				      unsigned int pte_flags, int const mmu_level, u64 pte)
+				      unsigned int const group_id, int const mmu_level, u64 pte)
 {
 	struct mgm_groups *const data = mgm_dev->data;
 
@@ -310,22 +309,7 @@ static u64 example_mgm_update_gpu_pte(struct memory_group_manager_device *const
 	if (WARN_ON(group_id >= MEMORY_GROUP_MANAGER_NR_GROUPS))
 		return pte;
 
-	/* If a page is mapped uncached on the CPU but cached on the GPU, it will be considered to
-	 * have Mismatched Memory Attributes (MMA), and the MMA_VIOLATION bit will be set in the
-	 * pte_flags argument.
-	 *
-	 * If the system requires consistent memory attributes external to the GPU, system
-	 * integrators must allocate one of the PBHA values (range 1-15) for this feature, and
-	 * specify the value either via the mma-wa-id devicetree property or via the mma_wa_id
-	 * module parameter, which is then passed into this function via the pbha_id parameter. The
-	 * GPU will continue to use cached transactions internally, but use non-cacheable
-	 * transactions externally. Note that system integrators may choose not to set the PBHA
-	 *  value here if their system does not require it.
-	 */
-	if (pte_flags & BIT(MMA_VIOLATION)) {
-		pr_warn_once("MMA violation! Applying PBHA override workaround to PTE\n");
-		pte |= ((u64)pbha_id << PTE_PBHA_SHIFT) & PTE_PBHA_MASK;
-	}
+	pte |= ((u64)group_id << PTE_PBHA_SHIFT) & PTE_PBHA_MASK;
 
 	/* Address could be translated into a different bus address here */
 	pte |= ((u64)1 << PTE_RES_BIT_MULTI_AS_SHIFT);
@@ -378,16 +362,6 @@ static vm_fault_t example_mgm_vmf_insert_pfn_prot(struct memory_group_manager_de
 	return fault;
 }
 
-static bool example_mgm_get_import_memory_cached_access_permitted(
-	struct memory_group_manager_device *mgm_dev,
-	struct memory_group_manager_import_data *import_data)
-{
-	CSTD_UNUSED(mgm_dev);
-	CSTD_UNUSED(import_data);
-
-	return true;
-}
-
 static int mgm_initialize_data(struct mgm_groups *mgm_data)
 {
 	int i;
@@ -434,8 +408,6 @@ static int memory_group_manager_probe(struct platform_device *pdev)
 	mgm_dev->ops.mgm_vmf_insert_pfn_prot = example_mgm_vmf_insert_pfn_prot;
 	mgm_dev->ops.mgm_update_gpu_pte = example_mgm_update_gpu_pte;
 	mgm_dev->ops.mgm_pte_to_original_pte = example_mgm_pte_to_original_pte;
-	mgm_dev->ops.mgm_get_import_memory_cached_access_permitted =
-		example_mgm_get_import_memory_cached_access_permitted;
 
 	mgm_data = kzalloc(sizeof(*mgm_data), GFP_KERNEL);
 	if (!mgm_data) {