chp2prs/synth.conf at master · asyncvlsi/chp2prs · GitHub

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#------------------------------------------------------------------------
#
# Synthesis Configuration File
#
#------------------------------------------------------------------------

begin synth

    # When implementing structure channels, the implementing type
    # will have an int channel port. This is the name of that port.
    # Now used for SDT as well.
    string struct_chan_name "CS"

    begin ring

        # Verbose ring synthesis output
        int verbose 0

        # NOTE:
        # The appropriate values for parameters here are
        # technology-specific and hence will have to
        # be updated when a new technology is used.
        begin bundled

            # Switch to trigger buffer on outputs of latches as they
            # may have high fanout. 0 for no buffer, >0 for buffer.
            int buffer_latch_reads 1

            # Number of different delay line types
            int delay_line_types 4

            # Define a continuous monotonically
            # increasing piece-wise linear
            # curve for delay vs. param (N),
            # as (x,y) pairs.
            # Last pair is typically two large values
            # corresponding to (inf,inf),
            # this is the largest allowed delay line

            # delay_params is x-axis (N)
            # delay_vals is y-axis (ps)
            # one for each datapath style

            # these are dummy numbers:

            int_table delay_params_DFF 0   5000     10000    50000     100000
            int_table delay_offsets_DFF 0   5000     10000    50000     100000
            real_table delay_vals_DFF  0.0 50000.0  100000.0 500000.0  1000000.0

            int_table delay_params_L 0   5000     10000    50000     100000
            int_table delay_offsets_L 0   5000     10000    50000     100000
            real_table delay_vals_L  0.0 50000.0  100000.0 500000.0  1000000.0

            int_table delay_params_L2P 0   5000     10000    50000     100000
            int_table delay_offsets_L2P 0   5000     10000    50000     100000
            real_table delay_vals_L2P  0.0 50000.0  100000.0 500000.0  1000000.0

            # Datapath delay values

            # Pulse width of pulse generator (ps)
            real pulse_width 210.0

            # Capture delay of a single latch (ps)
            # FF is essentially two of these in series
            real capture_delay 210.0

            # Merge-mux delays (ps):
            # Last value will be used if mux larger
            # than max-size defined here
            # inputs:                 2      3      4      5      6      7      8     9+
            real_table mux_delays 96.43 102.36 106.81 135.41 135.41 208.68 230.97 2000.0

            # OR-gate delays (ps):
            # Last value will be used if OR-gate larger
            # than max-size defined here
            # inputs:              0   1     2     3     4      5      6      7      8    9+
            real_table or_delays 0.0 0.0 66.12 86.47 89.87 108.46 119.20 139.24 213.70 500.0

            # These are for latency cost calculation for decomp
            # TODO: fill in correct numbers
            real send_delay 40.0
            real recv_delay 40.0
            real assn_delay  0.0

            # way:                  0   1    2    3    4    5    6    7    8   9+
            real_table sel_delays 0.0 0.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0

        end

    end

end