Merge branch 'main' into feat/tda4vm_plat_support

Signed-off-by: Vinit Puranik <kvp933.vinit@gmail.com>

Author: puranikvinit

CONTRIBUTORS

@@ -21,4 +21,4 @@ joaopeixoto13 <joaopeixotooficial@gmail.com>
 Miguel Silva <miguelafsilva5@gmail.com>
 Nikolai Kosmatov
 Bin Meng <bmeng.cn@gmail.com>
-noobsplzwin <huizhezheng@gmail.com>
+leon6002 <>

README.md

@@ -47,7 +47,7 @@ platforms is presented below:
 - [x] QEMU virt
 - [x] Arm Fixed Virtual Platforms
 - [x] Toradex Verdin iMX8M Plus (w/ Dahlia Carrier Board)
-- [ ] NXP S32G
+- [x] NXP S32G3
 - [x] BeagleBone AI-64
 
 **Armv7-A / Armv8-A AArch32**
@@ -60,7 +60,8 @@ platforms is presented below:
 **Armv8-R AArch32**
 - [x] Arm Fixed Virtual Platforms
 - [x] Arm MPS3-AN536
-- [ ] NXP S32Z/E
+- [x] Semidrive E3650
+- [x] NXP S32Z270
 - [ ] Renesas RZT2M
 
 **RISC-V RV64**

src/arch/armv8/armv8-r/cpus/core_impl.c

@@ -6,7 +6,8 @@
 #include <arch/sysregs.h>
 #include <arch/core_impl.h>
 
-#define ARMV8R_R52_PARTNUMBER 0xD13
+#define ARMV8R_R52_PARTNUMBER  0xD13
+#define ARMV8R_R52P_PARTNUMBER 0xD16
 
 /* Weak references to CPU implementation init functions */
 extern void cortex_r52_impl_init(void) __attribute__((weak));
@@ -18,7 +19,8 @@ void cpu_arch_core_impl_init(void)
     uint32_t part_num = MIDR_EL1_PARTNUM(midr);
 
     switch (part_num) {
-        case ARMV8R_R52_PARTNUMBER: /* Cortex-R52 */
+        case ARMV8R_R52_PARTNUMBER:  /* Cortex-R52 */
+        case ARMV8R_R52P_PARTNUMBER: /* Cortex-R52+ */
             if (cortex_r52_impl_init != NULL) {
                 cortex_r52_impl_init();
             }

src/arch/armv8/inc/arch/psci.h

@@ -40,6 +40,7 @@
 #define PSCI_INVALID_ADDRESS           (-1L)
 
 #define PSCI_VERSION_0_2               (2U)
+#define PSCI_VERSION_1_1               (0x10001)
 #define PSCI_GET_VERSION_MAJOR(ver)    (u16)((ver) >> 16)
 #define PSCI_GET_VERSION(major, minor) (((major) << 16) | (minor))
 

src/arch/armv8/inc/arch/smcc.h

@@ -8,6 +8,8 @@
 
 #define SMCC64_BIT              (0x40000000)
 
+#define SMCCC_VERSION           (0x80000000)
+
 #define SMCC_E_NOT_SUPPORTED    (-1)
 
 #define SMCC32_FID_STD_SRVC     (0x84000000)

src/arch/armv8/psci.c

@@ -11,6 +11,7 @@
 #include <mem.h>
 #include <cache.h>
 #include <config.h>
+#include <arch/smcc.h>
 
 enum { PSCI_MSG_ON };
 
@@ -170,8 +171,12 @@ static int32_t psci_features_handler(uint32_t feature_id)
         case PSCI_AFFINITY_INFO_SMC32:
         case PSCI_AFFINITY_INFO_SMC64:
         case PSCI_FEATURES:
+#ifdef PLAT_PSCI_SUPPORT_SMCCC_VERSION
+        case SMCCC_VERSION:
+#endif
             ret = PSCI_E_SUCCESS;
             break;
+
         default:
             ret = PSCI_E_NOT_SUPPORTED;
             break;
@@ -186,7 +191,7 @@ int32_t psci_smc_handler(uint32_t smc_fid, unsigned long x1, unsigned long x2, u
 
     switch (smc_fid) {
         case PSCI_VERSION:
-            ret = PSCI_VERSION_0_2;
+            ret = PSCI_VERSION_1_1;
             break;
 
         case PSCI_CPU_OFF:

src/arch/riscv/inc/arch/bao.h

@@ -29,14 +29,18 @@
 #define BAO_VM_BASE  (0xffffffe000000000)
 #define BAO_VAS_TOP  (0xfffffff000000000)
 #else
-// Because sv32 only lowest level only supports 4MiB pages, this should be enough for each section
-// otherwise we need allow for N shared PTEs for each section. For now, it seems to suffice. We also
-// are assuming, for now that all available physical memory resides in 0x0 - 0xefffffff of virtual
-// memory. Otherwise we need to implement a "highmem"-like mechanism.
+/**
+ * When using sv32 only the lowest level supports 4MiB pages. This should be
+ * enough for the shared regions, while the private region is left with 256 MiB.
+ * For now, it seems to suffice. Otherwise, we need allow for N shared PTEs for
+ * the shared sections. We are also assuming, for now, that all available
+ * physical memory resides in 0x0 - 0xefffffff of virtual memory. Otherwise we
+ * need to implement a "highmem"-like mechanism.
+ */
 #define BAO_VAS_BASE (0xc0000000)
-#define BAO_CPU_BASE (0xcf400000)
-#define BAO_VM_BASE  (0xcf800000)
-#define BAO_VAS_TOP  (0xcfc00000)
+#define BAO_CPU_BASE (0xc0400000)
+#define BAO_VM_BASE  (0xe0400000)
+#define BAO_VAS_TOP  (0xe0800000)
 #endif
 
 #define PAGE_SIZE        (0x1000)

src/arch/riscv/irqc/aia/imsic.c

@@ -67,23 +67,6 @@ void imsic_clr_pend(irqid_t intp_id)
     csrs_sireg_clear(1UL << imsic_eie_bit(intp_id));
 }
 
-/**
- * For now we only support 1 guest file per hart.
- * Should I remove the guest_file from the API?
- */
-void imsic_inject_pend(size_t guest_file, irqid_t intp_id)
-{
-    UNUSED_ARG(guest_file);
-
-    csrs_vsiselect_write(IMSIC_EIP + imsic_eie_index(intp_id));
-    csrs_vsireg_clear(1UL << imsic_eie_bit(intp_id));
-}
-
-void imsic_send_msi(cpuid_t target_cpu)
-{
-    imsic[target_cpu]->s_file.seteipnum_le = interrupts_ipi_id;
-}
-
 void imsic_handle(void)
 {
     /* Read STOPEI and write to it to claim the interrupt */

src/arch/riscv/irqc/aia/inc/imsic.h

@@ -25,8 +25,11 @@ struct imsic_intp_file_hw {
 
 struct imsic_global_hw {
     struct imsic_intp_file_hw s_file;
+    struct imsic_intp_file_hw guest_file;
 } __attribute__((__packed__, aligned(0x1000ULL)));
 
+extern volatile struct imsic_global_hw* imsic[PLAT_CPU_NUM];
+
 /**
  * @brief Initializes the IMSIC
  *
@@ -68,16 +71,28 @@ void imsic_set_enbl(irqid_t intp_id);
  *        Only little endian is supported.
  *
  * @param target_cpu The ID of the target CPU
+ * @param msi_id The MSI ID to be sent
  */
-void imsic_send_msi(cpuid_t target_cpu);
+static inline void imsic_send_msi(cpuid_t target_cpu, irqid_t msi_id)
+{
+    imsic[target_cpu]->s_file.seteipnum_le = msi_id;
+}
 
 /**
- * @brief Inject an interrupt into a guest.
+ * @brief Sends an MSI to the guest file of specified CPU with the specified IPI ID.
+ *
+ *        The function sends an MSI to the target CPU's guest file by setting the seteipnum_le
+ *        register in the IMSIC. The seteipnum_le register is used to specify the ID of the
+ *        interrupt being sent. Only little endian is supported. This function assume a single guest
+ *        interrupt file per hart.
  *
- * @param guest_file Guest interrupt file ID
- * @param intp_id Interrupt ID
+ * @param target_cpu The ID of the target CPU
+ * @param msi_id The MSI ID to be injected in the guest interrupt file
  */
-void imsic_inject_pend(size_t guest_file, irqid_t intp_id);
+static inline void imsic_send_guest_msi(cpuid_t target_cpu, irqid_t msi_id)
+{
+    imsic[target_cpu]->guest_file.seteipnum_le = msi_id;
+}
 
 /**
  * @brief Handles interrupts in the IMSIC.

src/arch/riscv/irqc/aia/inc/irqc.h

@@ -91,7 +91,8 @@ static inline irqid_t irqc_reserve(irqid_t pintp_id)
 
 static inline void irqc_send_ipi(cpuid_t target_cpu)
 {
-    imsic_send_msi(target_cpu);
+    extern irqid_t interrupts_ipi_id;
+    imsic_send_msi(target_cpu, interrupts_ipi_id);
 }
 
 static inline void irqc_handle(void)