diff --git a/src/arch/riscv/inc/arch/csrs.h b/src/arch/riscv/inc/arch/csrs.h
index c444f4c91..9024e2119 100644
--- a/src/arch/riscv/inc/arch/csrs.h
+++ b/src/arch/riscv/inc/arch/csrs.h
@@ -88,6 +88,13 @@
 #define SSTATUS_UPIE_BIT   (1UL << 4)
 #define SSTATUS_SPIE_BIT   (1UL << 5)
 #define SSTATUS_SPP_BIT    (1UL << 8)
+#define SSTATUS_VS_OFF     (9)
+#define SSTATUS_VS_LEN     (2)
+#define SSTATUS_VS_MSK     BIT_MASK(SSTATUS_VS_OFF, SSTATUS_VS_LEN)
+#define SSTATUS_VS_AOFF    (0)
+#define SSTATUS_VS_INITIAL (1UL << SSTATUS_VS_OFF)
+#define SSTATUS_VS_CLEAN   (2UL << SSTATUS_VS_OFF)
+#define SSTATUS_VS_DIRTY   (3UL << SSTATUS_VS_OFF)
 #define SSTATUS_FS_OFF     (13)
 #define SSTATUS_FS_LEN     (2)
 #define SSTATUS_FS_MSK     BIT_MASK(SSTATUS_FS_OFF, SSTATUS_FS_LEN)
diff --git a/src/arch/riscv/vm.c b/src/arch/riscv/vm.c
index 1a537ef12..8d4619ce5 100644
--- a/src/arch/riscv/vm.c
+++ b/src/arch/riscv/vm.c
@@ -45,6 +45,9 @@ void vcpu_arch_reset(struct vcpu* vcpu, vaddr_t entry)
     }
 
     vcpu->regs.sstatus = SSTATUS_SPP_BIT | SSTATUS_FS_DIRTY | SSTATUS_XS_DIRTY;
+    if (CPU_HAS_EXTENSION(CPU_EXT_V)) {
+        vcpu->regs.sstatus |= SSTATUS_VS_DIRTY;
+    }
     vcpu->regs.sepc = entry;
     vcpu->regs.a0 = vcpu->arch.hart_id = vcpu->id;
     vcpu->regs.a1 = 0; // according to sbi it should be the dtb load address
@@ -52,6 +55,9 @@ void vcpu_arch_reset(struct vcpu* vcpu, vaddr_t entry)
     csrs_hcounteren_write(HCOUNTEREN_TM);
     csrs_htimedelta_write(0);
     csrs_vsstatus_write(SSTATUS_SD | SSTATUS_FS_DIRTY | SSTATUS_XS_DIRTY);
+    if (CPU_HAS_EXTENSION(CPU_EXT_V)) {
+        csrs_vsstatus_set(SSTATUS_VS_DIRTY);
+    }
     csrs_hie_write(0);
     csrs_vstvec_write(0);
     csrs_vsscratch_write(0);
diff --git a/src/platform/qemu-riscv64-virt/inc/plat/platform.h b/src/platform/qemu-riscv64-virt/inc/plat/platform.h
index 8d4215222..afd31bb15 100644
--- a/src/platform/qemu-riscv64-virt/inc/plat/platform.h
+++ b/src/platform/qemu-riscv64-virt/inc/plat/platform.h
@@ -9,6 +9,7 @@
 #include <drivers/sbi_uart.h>
 
 #define CPU_EXT_SSTC 1
+#define CPU_EXT_V    0
 
 #define IPIC_SBI     (1)
 #define IPIC_ACLINT  (2)