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RISC-V Vector Extension Support #351

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RISC-V Vector Extension Support #351

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7 changes: 7 additions & 0 deletions src/arch/riscv/inc/arch/csrs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -88,6 +88,13 @@
#define SSTATUS_UPIE_BIT (1UL << 4)
#define SSTATUS_SPIE_BIT (1UL << 5)
#define SSTATUS_SPP_BIT (1UL << 8)
#define SSTATUS_VS_OFF (9)
#define SSTATUS_VS_LEN (2)
#define SSTATUS_VS_MSK BIT_MASK(SSTATUS_VS_OFF, SSTATUS_VS_LEN)
#define SSTATUS_VS_AOFF (0)
#define SSTATUS_VS_INITIAL (1UL << SSTATUS_VS_OFF)
#define SSTATUS_VS_CLEAN (2UL << SSTATUS_VS_OFF)
#define SSTATUS_VS_DIRTY (3UL << SSTATUS_VS_OFF)
#define SSTATUS_FS_OFF (13)
#define SSTATUS_FS_LEN (2)
#define SSTATUS_FS_MSK BIT_MASK(SSTATUS_FS_OFF, SSTATUS_FS_LEN)
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6 changes: 6 additions & 0 deletions src/arch/riscv/vm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -45,13 +45,19 @@ void vcpu_arch_reset(struct vcpu* vcpu, vaddr_t entry)
}

vcpu->regs.sstatus = SSTATUS_SPP_BIT | SSTATUS_FS_DIRTY | SSTATUS_XS_DIRTY;
if (CPU_HAS_EXTENSION(CPU_EXT_V)) {
vcpu->regs.sstatus |= SSTATUS_VS_DIRTY;
}
vcpu->regs.sepc = entry;
vcpu->regs.a0 = vcpu->arch.hart_id = vcpu->id;
vcpu->regs.a1 = 0; // according to sbi it should be the dtb load address

csrs_hcounteren_write(HCOUNTEREN_TM);
csrs_htimedelta_write(0);
csrs_vsstatus_write(SSTATUS_SD | SSTATUS_FS_DIRTY | SSTATUS_XS_DIRTY);
if (CPU_HAS_EXTENSION(CPU_EXT_V)) {
csrs_vsstatus_set(SSTATUS_VS_DIRTY);
}
csrs_hie_write(0);
csrs_vstvec_write(0);
csrs_vsscratch_write(0);
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1 change: 1 addition & 0 deletions src/platform/qemu-riscv64-virt/inc/plat/platform.h
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Expand Up @@ -9,6 +9,7 @@
#include <drivers/sbi_uart.h>

#define CPU_EXT_SSTC 1
#define CPU_EXT_V 0

#define IPIC_SBI (1)
#define IPIC_ACLINT (2)
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