[Hardware][RISC-V] Add riscv64 support

[langc23]

The purpose of this PR is to support RISC-V architectures.

[langc23]

@benfred Hello, we hope the PR could merged into the mainline, but need your review and start workflow. Could you please take a time? Thanks.

[langc23]

@benfred @yihong0618 @peytondmurray @zanieb Hello, we hope the PR could merged into the mainline, but need your review and start workflow. Could you please take a time? Thanks.

[langc23]

@benfred @yihong0618 @peytondmurray @zanieb Hello, the purpose of this PR is to support RISC-V architectures. We hope the PR could merged into the mainline, but need your review and start workflow. Could you please take a time? Thanks.

[peytondmurray]

@langc23 Sorry, I'm not a maintainer, just an occasional contributor 🤷

[yihong0618]

@langc23 Sorry, me too...

[yihong0618]

@langc23 just checked its MIT License if you indeed need it, you can fork it and publish to pypi yourself

maybe named py-spy-fork and waiting for the maintainer not so busy time

[langc23]

@langc23 just checked its MIT License if you indeed need it, you can fork it and publish to pypi yourself

maybe named py-spy-fork and waiting for the maintainer not so busy time

Thank you for your suggestions. But I also hope it could merged into the mainline.

[benfred]

How is this tested? Can we verify that this works in CI against a risc64 cpu, and with more python versions than just v3.11.6 ?

[benfred]

Why do you need a separate v3.11.6 bindings here? We've managed to use the existing v3.11 bindings for x86_64/aarch64/armv7/i686 cpu's - and I'm curious why this won't work for risc64?

Also does this mean that this risc support will only work with python 3.11?

[langc23]

Because the existing binding does not specify the RISC-V architecture. But we add [cfg(all(target_os = "linux", target_arch = "riscv64"))].

It is also possible to modify it to support x86 and other architectures, but since the Python version on RISC-V 64 is generally 3.11.6, I chose this version.

[benfred]

How is this v3_11_6 module being used? We've implemented the traits for all the bindings - and just importing the module on its own won't do much

[langc23]

This module is adapted for the RISC-V 64-bit architecture, e.g. openEuler 24.03.

[benfred]

My point was that this module is dead code - you've generated the bindings, but aren't using them anywhere.

If this actually was necessary you'd have to update places like

py-spy/src/python_interpreters.rs

Line 691 in 194bf64

Python3Impl!(v3_11_0);

and

py-spy/src/python_spy.rs

Lines 165 to 169 in 194bf64

	Version {
	major: 3,
	minor: 11,
	..
	} => self._get_stack_traces::<v3_11_0::_is>(),

like the actual v3_11_0 code does to use this file

This entire file needs deleted from the PR as its not used anywhere.

[langc23]

Yes, you are right. I have changed the commit, please review it again. Thanks!