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This repository was archived by the owner on Mar 7, 2026. It is now read-only.

Commit e9ace3a

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incorporate feedback on patch-in-progress
Signed-off-by: Sean Cross <sean@xobs.io>
1 parent ccb9122 commit e9ace3a

2 files changed

Lines changed: 11 additions & 12 deletions

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src/include/buffer_utils.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,6 @@ static inline uint64_t read_le8(const uint8_t *const buffer, const size_t offset
116116
((uint64_t)buffer[offset + 1] << 8U) | buffer[offset + 0];
117117
}
118118

119-
120119
static inline size_t write_char(char *const buffer, const size_t buffer_size, const size_t offset, const char c)
121120
{
122121
if (buffer && offset < buffer_size)

src/target/cortexar.c

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -895,9 +895,8 @@ static target_s *cortexar_probe(
895895
cortexar_run_insn(target, ARM_MRS_R0_CPSR_INSN);
896896
priv->core_regs.cpsr = cortexar_core_reg_read(target, 0U);
897897
cortexar_core_reg_write(target, 0U, r0);
898-
if (priv->core_regs.cpsr & CORTEXAR_CPSR_BE) {
898+
if (priv->core_regs.cpsr & CORTEXAR_CPSR_BE)
899899
target->target_options |= TOPT_FLAVOUR_BE;
900-
}
901900

902901
return target;
903902
}
@@ -935,9 +934,11 @@ bool cortexr_probe(adiv5_access_port_s *const ap, const target_addr_t base_addre
935934
if (!target)
936935
return false;
937936

938-
// TI omitted the designer code on TMS570.
939-
if (target->designer_code == 0) {
940-
PROBE(ti_tms570_probe);
937+
switch (target->designer_code) {
938+
/* TI omitted the designer code on TMS570 */
939+
case 0:
940+
PROBE(ti_tms570_probe);
941+
break;
941942
}
942943

943944
#if CONFIG_BMDA == 0
@@ -1224,11 +1225,10 @@ static inline bool cortexar_mem_write_fast(target_s *const target, const uint32_
12241225
/* Write each of the uint32_t's checking for failure */
12251226
for (size_t offset = 0; offset < count; ++offset) {
12261227
uint32_t value;
1227-
if (target->target_options & TOPT_FLAVOUR_BE) {
1228-
value = read_be4((const void *const)src, offset * 4);
1229-
} else {
1230-
value = read_le4((const void *const)src, offset * 4);
1231-
}
1228+
if (target->target_options & TOPT_FLAVOUR_BE)
1229+
value = read_be4((const void *)src, offset * 4U);
1230+
else
1231+
value = read_le4((const void *)src, offset * 4U);
12321232
if (!cortexar_run_write_insn(target, ARM_STC_DTRRX_R0_POSTINC4_INSN, value))
12331233
return false; /* Propagate failure if it happens */
12341234
}
@@ -1444,7 +1444,7 @@ static size_t cortexar_reg_read(target_s *const target, const uint32_t reg, void
14441444
value = read_be8(reg_ptr, 0);
14451445
else
14461446
value = read_le8(reg_ptr, 0);
1447-
write_le4(data, 0, value);
1447+
write_le8(data, 0, value);
14481448
break;
14491449
}
14501450
}

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